Commit cc86630f authored by Jeff Young's avatar Jeff Young
Browse files

Start pulling new DRC engine into Kicad.

parent 6b4a6f4d
......@@ -236,6 +236,8 @@ set( PCBNEW_DRC_SRCS
drc/drc_textvar_tester.cpp
drc/drc.cpp
drc/drc_clearance_test_functions.cpp
drc/drc_engine.cpp
drc/drc_test_provider.cpp
drc/drc_rule_parser.cpp
drc/footprint_tester.cpp
)
......
......@@ -156,8 +156,8 @@ bool BOARD_CONNECTED_ITEM::GetRuleClearance( BOARD_ITEM* aItem, PCB_LAYER_ID aLa
int* aClearance, wxString* aSource,
REPORTER* aReporter ) const
{
const DRC_CONSTRAINT* constraint = GetConstraint( this, aItem, DRC_RULE_ID_CLEARANCE, aLayer,
aSource, aReporter );
const DRC_CONSTRAINT* constraint = GetConstraint( this, aItem, DRC_CONSTRAINT_TYPE_CLEARANCE,
aLayer, aSource, aReporter );
if( constraint )
{
......
......@@ -836,7 +836,7 @@ int BOARD_DESIGN_SETTINGS::GetBiggestClearanceValue()
{
for( const DRC_CONSTRAINT& constraint : rule->m_Constraints )
{
if( constraint.m_Type == DRC_RULE_ID_CLEARANCE )
if( constraint.m_Type == DRC_CONSTRAINT_TYPE_CLEARANCE )
clearance = std::max( clearance, constraint.m_Value.Min() );
}
}
......
......@@ -139,8 +139,9 @@ void TRACK::GetWidthConstraints( int* aMin, int* aMax, wxString* aSource ) const
// Not currently implemented
// LEVEL 2: Rules
const DRC_CONSTRAINT* constraint = GetConstraint( this, nullptr, DRC_RULE_ID_TRACK, m_Layer,
aSource );
const DRC_CONSTRAINT* constraint = GetConstraint( this, nullptr,
DRC_CONSTRAINT_TYPE_TRACK_WIDTH,
m_Layer, aSource );
if( constraint )
{
......@@ -177,8 +178,9 @@ int VIA::GetMinAnnulus( PCB_LAYER_ID aLayer, wxString* aSource ) const
return 0;
}
const DRC_CONSTRAINT* constraint = GetConstraint( this, nullptr, DRC_RULE_ID_ANNULUS, aLayer,
aSource );
const DRC_CONSTRAINT* constraint = GetConstraint( this, nullptr,
DRC_CONSTRAINT_TYPE_ANNULUS_WIDTH,
aLayer, aSource );
if( constraint )
{
......
......@@ -372,58 +372,58 @@ int ZONE_CONTAINER::GetKeepouts( PCB_LAYER_ID aLayer, std::map<int, wxString>* a
source = _( "zone properties" );
if( m_doNotAllowTracks )
setFlag( DISALLOW_TRACKS );
setFlag( DRC_DISALLOW_TRACKS );
if( m_doNotAllowVias )
setFlag( DISALLOW_VIAS );
setFlag( DRC_DISALLOW_VIAS );
if( m_doNotAllowPads )
setFlag( DISALLOW_PADS );
setFlag( DRC_DISALLOW_PADS );
if( m_doNotAllowFootprints )
setFlag( DISALLOW_FOOTPRINTS );
setFlag( DRC_DISALLOW_FOOTPRINTS );
if( m_doNotAllowCopperPour )
setFlag( DISALLOW_ZONES );
setFlag( DRC_DISALLOW_ZONES );
}
const DRC_CONSTRAINT* constraint = GetConstraint( this, nullptr, DRC_RULE_ID_DISALLOW, aLayer,
&source );
const DRC_CONSTRAINT* constraint = GetConstraint( this, nullptr, DRC_CONSTRAINT_TYPE_DISALLOW,
aLayer, &source );
if( constraint )
{
if( aSources )
source = wxString::Format( _( "'%s' rule" ), source );
if( ( constraint->m_DisallowFlags & DISALLOW_VIAS ) > 0 )
setFlag( DISALLOW_VIAS );
if( ( constraint->m_DisallowFlags & DRC_DISALLOW_VIAS ) > 0 )
setFlag( DRC_DISALLOW_VIAS );
if( ( constraint->m_DisallowFlags & DISALLOW_MICRO_VIAS ) > 0 )
setFlag( DISALLOW_MICRO_VIAS );
if( ( constraint->m_DisallowFlags & DRC_DISALLOW_MICRO_VIAS ) > 0 )
setFlag( DRC_DISALLOW_MICRO_VIAS );
if( ( constraint->m_DisallowFlags & DISALLOW_BB_VIAS ) > 0 )
setFlag( DISALLOW_BB_VIAS );
if( ( constraint->m_DisallowFlags & DRC_DISALLOW_BB_VIAS ) > 0 )
setFlag( DRC_DISALLOW_BB_VIAS );
if( ( constraint->m_DisallowFlags & DISALLOW_TRACKS ) > 0 )
setFlag( DISALLOW_TRACKS );
if( ( constraint->m_DisallowFlags & DRC_DISALLOW_TRACKS ) > 0 )
setFlag( DRC_DISALLOW_TRACKS );
if( ( constraint->m_DisallowFlags & DISALLOW_PADS ) > 0 )
setFlag( DISALLOW_PADS );
if( ( constraint->m_DisallowFlags & DRC_DISALLOW_PADS ) > 0 )
setFlag( DRC_DISALLOW_PADS );
if( ( constraint->m_DisallowFlags & DISALLOW_ZONES ) > 0 )
setFlag( DISALLOW_ZONES );
if( ( constraint->m_DisallowFlags & DRC_DISALLOW_ZONES ) > 0 )
setFlag( DRC_DISALLOW_ZONES );
if( ( constraint->m_DisallowFlags & DISALLOW_TEXTS ) > 0 )
setFlag( DISALLOW_TEXTS );
if( ( constraint->m_DisallowFlags & DRC_DISALLOW_TEXTS ) > 0 )
setFlag( DRC_DISALLOW_TEXTS );
if( ( constraint->m_DisallowFlags & DISALLOW_GRAPHICS ) > 0 )
setFlag( DISALLOW_GRAPHICS );
if( ( constraint->m_DisallowFlags & DRC_DISALLOW_GRAPHICS ) > 0 )
setFlag( DRC_DISALLOW_GRAPHICS );
if( ( constraint->m_DisallowFlags & DISALLOW_HOLES ) > 0 )
setFlag( DISALLOW_HOLES );
if( ( constraint->m_DisallowFlags & DRC_DISALLOW_HOLES ) > 0 )
setFlag( DRC_DISALLOW_HOLES );
if( ( constraint->m_DisallowFlags & DISALLOW_FOOTPRINTS ) > 0 )
setFlag( DISALLOW_FOOTPRINTS );
if( ( constraint->m_DisallowFlags & DRC_DISALLOW_FOOTPRINTS ) > 0 )
setFlag( DRC_DISALLOW_FOOTPRINTS );
}
return keepouts;
......
......@@ -29,7 +29,7 @@
#include <tools/pcb_actions.h>
#include <tracks_cleaner.h>
#include <drc/drc_item.h>
#include <drc/drc_provider.h>
#include <drc/drc_results_provider.h>
#include <tools/zone_filler_tool.h>
DIALOG_CLEANUP_TRACKS_AND_VIAS::DIALOG_CLEANUP_TRACKS_AND_VIAS( PCB_EDIT_FRAME* aParentFrame ) :
......
......@@ -39,38 +39,41 @@
/// DRC error codes:
enum PCB_DRC_CODE {
DRCE_FIRST = 1,
DRCE_UNCONNECTED_ITEMS = DRCE_FIRST, ///< items are unconnected
DRCE_SHORTING_ITEMS, ///< items short two nets but are not a net tie
DRCE_ALLOWED_ITEMS, ///< a disallowed item has been used
DRCE_CLEARANCE, ///< items are too close together
DRCE_TRACKS_CROSSING, ///< tracks are crossing
DRCE_COPPER_EDGE_CLEARANCE, ///< a copper item is too close to the board edge
DRCE_ZONES_INTERSECT, ///< copper area outlines intersect
DRCE_ZONE_HAS_EMPTY_NET, ///< copper area has a net but no pads in nets, which is suspicious
DRCE_DANGLING_VIA, ///< via which isn't connected to anything
DRCE_DANGLING_TRACK, ///< track with at least one end not connected to anything
DRCE_DRILLED_HOLES_TOO_CLOSE, ///< overlapping drilled holes break drill bits
DRCE_TRACK_WIDTH, ///< Track width is too small or too large
DRCE_TOO_SMALL_VIA, ///< Too small via size
DRCE_VIA_ANNULUS, ///< Via size and drill leave annulus too small or too large
DRCE_TOO_SMALL_DRILL, ///< Too small via or pad drill
DRCE_VIA_HOLE_BIGGER, ///< via's hole is bigger than its diameter
DRCE_PADSTACK, ///< something is wrong with a pad or via stackup
DRCE_TOO_SMALL_MICROVIA, ///< Too small micro via size
DRCE_TOO_SMALL_MICROVIA_DRILL, ///< Too small micro via drill
DRCE_KEEPOUT, ///< A disallowed object is inside a keepout
DRCE_OVERLAPPING_FOOTPRINTS, ///< footprint courtyards overlap
DRCE_MISSING_COURTYARD, ///< footprint has no courtyard defined
DRCE_MALFORMED_COURTYARD, ///< footprint has a courtyard but malformed
///< (not convertible to a closed polygon with holes)
DRCE_UNCONNECTED_ITEMS = DRCE_FIRST, // items are unconnected
DRCE_SHORTING_ITEMS, // items short two nets but are not a net-tie
DRCE_ALLOWED_ITEMS, // a disallowed item has been used
DRCE_CLEARANCE, // items are too close together
DRCE_TRACKS_CROSSING, // tracks are crossing
DRCE_COPPER_EDGE_CLEARANCE, // a copper item is too close to the board edge
DRCE_ZONES_INTERSECT, // copper area outlines intersect
DRCE_ZONE_HAS_EMPTY_NET, // copper area has a net but no pads in nets, which is suspicious
DRCE_DANGLING_VIA, // via which isn't connected to anything
DRCE_DANGLING_TRACK, // track with at least one end not connected to anything
DRCE_DRILLED_HOLES_TOO_CLOSE, // overlapping drilled holes break drill bits
DRCE_HOLE_CLEARANCE, //
DRCE_TRACK_WIDTH, // Track width is too small or too large
DRCE_TOO_SMALL_VIA, // Too small via size
DRCE_ANNULUS, // Via size and drill leave annulus too small or too large
DRCE_TOO_SMALL_DRILL, // Too small via or pad drill
DRCE_VIA_HOLE_BIGGER, // via's hole is bigger than its diameter
DRCE_VIA_DIAMETER, // Via diameter checks (min/max)
DRCE_PADSTACK, // something is wrong with a pad or via stackup
DRCE_TOO_SMALL_MICROVIA, // Too small micro via size
DRCE_TOO_SMALL_MICROVIA_DRILL, // Too small micro via drill
DRCE_KEEPOUT, // A disallowed object is inside a keepout
DRCE_OVERLAPPING_FOOTPRINTS, // footprint courtyards overlap
DRCE_MISSING_COURTYARD, // footprint has no courtyard defined
DRCE_MALFORMED_COURTYARD, // footprint has a courtyard but malformed
// (not convertible to a closed polygon with holes)
DRCE_PTH_IN_COURTYARD,
DRCE_NPTH_IN_COURTYARD,
DRCE_DISABLED_LAYER_ITEM, ///< item on a disabled layer
DRCE_INVALID_OUTLINE, ///< invalid board outline
DRCE_MISSING_FOOTPRINT, ///< footprint not found for netlist item
DRCE_DUPLICATE_FOOTPRINT, ///< more than one footprints found for netlist item
DRCE_EXTRA_FOOTPRINT, ///< netlist item not found for footprint
DRCE_NET_CONFLICT, ///< pad net doesn't match netlist
DRCE_DISABLED_LAYER_ITEM, // item on a disabled layer
DRCE_INVALID_OUTLINE, // invalid board outline
DRCE_MISSING_FOOTPRINT, // footprint not found for netlist item
DRCE_DUPLICATE_FOOTPRINT, // more than one footprints found for netlist item
DRCE_EXTRA_FOOTPRINT, // netlist item not found for footprint
DRCE_NET_CONFLICT, // pad net doesn't match netlist
DRCE_UNRESOLVED_VARIABLE,
......
......@@ -43,7 +43,7 @@ void DRC::doSingleViaDRC( BOARD_COMMIT& aCommit, VIA* aRefVia )
{
if( aRefVia->GetWidth() < bds.m_MicroViasMinSize )
{
std::shared_ptr<DRC_ITEM> drcItem = DRC_ITEM::Create( DRCE_VIA_ANNULUS );
std::shared_ptr<DRC_ITEM> drcItem = DRC_ITEM::Create( DRCE_ANNULUS );
m_msg.Printf( drcItem->GetErrorText() + _( " (board minimum %s; actual %s)" ),
MessageTextFromValue( userUnits(), bds.m_MicroViasMinSize, true ),
......@@ -60,7 +60,7 @@ void DRC::doSingleViaDRC( BOARD_COMMIT& aCommit, VIA* aRefVia )
{
if( aRefVia->GetWidth() < bds.m_ViasMinSize )
{
std::shared_ptr<DRC_ITEM> drcItem = DRC_ITEM::Create( DRCE_VIA_ANNULUS );
std::shared_ptr<DRC_ITEM> drcItem = DRC_ITEM::Create( DRCE_ANNULUS );
m_msg.Printf( drcItem->GetErrorText() + _( " (board minimum %s; actual %s)" ),
MessageTextFromValue( userUnits(), bds.m_ViasMinSize, true ),
......@@ -231,7 +231,7 @@ void DRC::doTrackDrc( BOARD_COMMIT& aCommit, TRACK* aRefSeg, TRACKS::iterator aS
{
if( viaAnnulus < minAnnulus )
{
std::shared_ptr<DRC_ITEM> drcItem = DRC_ITEM::Create( DRCE_VIA_ANNULUS );
std::shared_ptr<DRC_ITEM> drcItem = DRC_ITEM::Create( DRCE_ANNULUS );
m_msg.Printf( _( "Via annulus too small (%s %s; actual %s)" ),
m_clearanceSource,
......@@ -255,7 +255,7 @@ void DRC::doTrackDrc( BOARD_COMMIT& aCommit, TRACK* aRefSeg, TRACKS::iterator aS
if( viaAnnulus < minAnnulus )
{
std::shared_ptr<DRC_ITEM> drcItem = DRC_ITEM::Create( DRCE_VIA_ANNULUS );
std::shared_ptr<DRC_ITEM> drcItem = DRC_ITEM::Create( DRCE_ANNULUS );
m_msg.Printf( _( "Via annulus too small (%s %s; actual %s)" ),
m_clearanceSource,
......@@ -303,8 +303,8 @@ void DRC::doTrackDrc( BOARD_COMMIT& aCommit, TRACK* aRefSeg, TRACKS::iterator aS
{
const SHAPE_SEGMENT* slot = pad->GetEffectiveHoleShape();
const DRC_CONSTRAINT* constraint = GetConstraint( aRefSeg, pad,
DRC_RULE_ID_CLEARANCE, aLayer,
&m_clearanceSource );
DRC_CONSTRAINT_TYPE_CLEARANCE,
aLayer, &m_clearanceSource );
int minClearance;
int actual;
......
......@@ -35,7 +35,7 @@
#include <drc/drc_item.h>
DRC_COURTYARD_TESTER::DRC_COURTYARD_TESTER( MARKER_HANDLER aMarkerHandler ) :
DRC_TEST_PROVIDER( std::move( aMarkerHandler ) )
LEGACY_DRC_TEST_PROVIDER( std::move( aMarkerHandler ) )
{
}
......
......@@ -25,12 +25,12 @@
#ifndef DRC_COURTYARD_OVERLAP__H
#define DRC_COURTYARD_OVERLAP__H
#include <drc/drc_provider.h>
#include <drc/drc_results_provider.h>
class BOARD;
class DRC_COURTYARD_TESTER : public DRC_TEST_PROVIDER
class DRC_COURTYARD_TESTER : public LEGACY_DRC_TEST_PROVIDER
{
public:
DRC_COURTYARD_TESTER( MARKER_HANDLER aMarkerHandler );
......
......@@ -31,7 +31,7 @@
DRC_DRILLED_HOLE_TESTER::DRC_DRILLED_HOLE_TESTER( MARKER_HANDLER aMarkerHandler ) :
DRC_TEST_PROVIDER( std::move( aMarkerHandler ) ),
LEGACY_DRC_TEST_PROVIDER( std::move( aMarkerHandler ) ),
m_units( EDA_UNITS::MILLIMETRES ),
m_board( nullptr ),
m_largestRadius( 0 )
......@@ -94,7 +94,7 @@ bool DRC_DRILLED_HOLE_TESTER::checkPad( D_PAD* aPad )
if( !bds.Ignore( DRCE_TOO_SMALL_DRILL ) )
{
int minHole;
const DRC_CONSTRAINT* constraint = GetConstraint( aPad, nullptr, DRC_RULE_ID_HOLE_SIZE,
const DRC_CONSTRAINT* constraint = GetConstraint( aPad, nullptr, DRC_CONSTRAINT_TYPE_HOLE_SIZE,
layer, &m_source );
if( constraint )
......@@ -145,7 +145,7 @@ bool DRC_DRILLED_HOLE_TESTER::checkVia( VIA* via )
if( !bds.Ignore( DRCE_TOO_SMALL_DRILL ) )
{
int minHole;
const DRC_CONSTRAINT* constraint = GetConstraint( via, nullptr, DRC_RULE_ID_HOLE_SIZE,
const DRC_CONSTRAINT* constraint = GetConstraint( via, nullptr, DRC_CONSTRAINT_TYPE_HOLE_SIZE,
layer, &m_source );
if( constraint )
......@@ -197,7 +197,7 @@ bool DRC_DRILLED_HOLE_TESTER::checkMicroVia( VIA* via )
if( !bds.Ignore( DRCE_TOO_SMALL_MICROVIA_DRILL ) )
{
int minHole;
const DRC_CONSTRAINT* constraint = GetConstraint( via, nullptr, DRC_RULE_ID_HOLE_SIZE,
const DRC_CONSTRAINT* constraint = GetConstraint( via, nullptr, DRC_CONSTRAINT_TYPE_HOLE_SIZE,
layer, &m_source );
if( constraint )
......
......@@ -25,14 +25,14 @@
#ifndef DRC_DRILLED_HOLE_TESTER__H
#define DRC_DRILLED_HOLE_TESTER__H
#include <drc/drc_provider.h>
#include <drc/drc_results_provider.h>
class BOARD;
class BOARD_ITEM;
class DRC_DRILLED_HOLE_TESTER : public DRC_TEST_PROVIDER
class DRC_DRILLED_HOLE_TESTER : public LEGACY_DRC_TEST_PROVIDER
{
public:
DRC_DRILLED_HOLE_TESTER( MARKER_HANDLER aMarkerHandler );
......
This diff is collapsed.
......@@ -34,8 +34,8 @@
#include <tools/pcb_tool_base.h>
#include <vector>
#include <drc/drc_rule.h>
#include <drc_proto/drc_rule.h>
class BOARD_DESIGN_SETTINGS;
class PCB_EDIT_FRAME;
......@@ -67,13 +67,10 @@ void drcPrintDebugMessage( int level, wxString msg, const char *function, int li
//#define drc_dbg(level, fmt, ...) \
// wxLogTrace("DUPA", fmt, __VA_ARGS__);
namespace test
{
class DRC_RULE_CONDITION;
class DRC_ITEM;
class DRC_RULE;
class DRC_TEST_PROVIDER;
class LEGACY_DRC_TEST_PROVIDER;
class DRC_CONSTRAINT;
enum DRC_CONSTRAINT_QUERY_T
......@@ -82,47 +79,6 @@ enum DRC_CONSTRAINT_QUERY_T
// fixme: more to come I guess...
};
/// DRC error codes:
enum PCB_DRC_CODE
{
DRCE_FIRST = 1,
DRCE_UNCONNECTED_ITEMS = DRCE_FIRST, ///< items are unconnected
DRCE_SHORTING_ITEMS, ///< items shorting two nets but not a net-tie
DRCE_ALLOWED_ITEMS, ///< a disallowed item has been used
DRCE_CLEARANCE, ///< items are too close together
DRCE_TRACKS_CROSSING, ///< tracks are crossing
DRCE_COPPER_EDGE_CLEARANCE, ///< a copper item is too close to the board edge
DRCE_ZONES_INTERSECT, ///< copper area outlines intersect
DRCE_ZONE_HAS_EMPTY_NET, ///< copper area has a net but no pads in nets, which is suspicious
DRCE_DANGLING_VIA, ///< via which isn't connected to anything
DRCE_DANGLING_TRACK, ///< track with at least one end not connected to anything
DRCE_HOLE_CLEARANCE, ///< overlapping drilled holes break drill bits
DRCE_TRACK_WIDTH, ///< Track width is too small or too large
DRCE_TOO_SMALL_VIA, ///< Too small via size
DRCE_ANNULUS, ///< Via size and drill leave annulus too small or too large
DRCE_TOO_SMALL_DRILL, ///< Too small via or pad drill
DRCE_VIA_HOLE_BIGGER, ///< via's hole is bigger than its diameter
DRCE_PADSTACK, ///< something is wrong with a pad or via stackup
DRCE_TOO_SMALL_MICROVIA, ///< Too small micro via size
DRCE_TOO_SMALL_MICROVIA_DRILL, ///< Too small micro via drill
DRCE_KEEPOUT, ///< A disallowed object is inside a keepout
DRCE_OVERLAPPING_FOOTPRINTS, ///< footprint courtyards overlap
DRCE_MISSING_COURTYARD, ///< footprint has no courtyard defined
DRCE_MALFORMED_COURTYARD, ///< footprint has a courtyard but malformed
///< (not convertible to a closed polygon with holes)
DRCE_PTH_IN_COURTYARD,
DRCE_NPTH_IN_COURTYARD,
DRCE_DISABLED_LAYER_ITEM, ///< item on a disabled layer
DRCE_INVALID_OUTLINE, ///< invalid board outline
DRCE_MISSING_FOOTPRINT, ///< footprint not found for netlist item
DRCE_DUPLICATE_FOOTPRINT, ///< more than one footprints found for netlist item
DRCE_EXTRA_FOOTPRINT, ///< netlist item not found for footprint
DRCE_UNRESOLVED_VARIABLE,
DRCE_VIA_DIAMETER, ///< Via diameter checks (min/max)
DRCE_LAST = DRCE_UNRESOLVED_VARIABLE
};
class DRC_REPORT
{
......@@ -197,7 +153,6 @@ public:
m_reporter = aReporter;
}
bool LoadRules( wxFileName aPath );
void RunTests();
void SetErrorLimit( int aLimit );
......@@ -212,14 +167,13 @@ public:
return m_board;
}
const DRC_CONSTRAINT& EvalRulesForItems( DRC_CONSTRAINT_TYPE_T ruleID, BOARD_ITEM* a,
BOARD_ITEM* b = nullptr,
PCB_LAYER_ID aLayer = UNDEFINED_LAYER );
std::vector<DRC_CONSTRAINT> QueryConstraintsById( DRC_CONSTRAINT_TYPE_T ruleID );
const DRC_CONSTRAINT& EvalRulesForItems(
DRC_CONSTRAINT_TYPE_T ruleID, BOARD_ITEM* a, BOARD_ITEM* b = nullptr, PCB_LAYER_ID aLayer = UNDEFINED_LAYER );
std::vector<DRC_CONSTRAINT> QueryConstraintsById( test::DRC_CONSTRAINT_TYPE_T ruleID );
bool HasCorrectRulesForId( test::DRC_CONSTRAINT_TYPE_T ruleID );
bool HasCorrectRulesForId( DRC_CONSTRAINT_TYPE_T ruleID );
EDA_UNITS UserUnits() const
{
......@@ -235,12 +189,11 @@ public:
std::shared_ptr<DRC_REPORT> GetReport() const { return m_drcReport; }
bool QueryWorstConstraint( DRC_CONSTRAINT_TYPE_T aRuleId, test::DRC_CONSTRAINT& aConstraint, DRC_CONSTRAINT_QUERY_T aQueryType );
bool QueryWorstConstraint( DRC_CONSTRAINT_TYPE_T aRuleId, DRC_CONSTRAINT& aConstraint,
DRC_CONSTRAINT_QUERY_T aQueryType );
private:
void addRule( test::DRC_RULE* rule )
void addRule( DRC_RULE* rule )
{
m_rules.push_back(rule);
}
......@@ -249,42 +202,40 @@ private:
struct CONSTRAINT_WITH_CONDITIONS
{
std::vector<test::DRC_RULE_CONDITION*> conditions;
test::DRC_RULE* parentRule;
test::DRC_CONSTRAINT constraint;
std::vector<DRC_RULE_CONDITION*> conditions;
DRC_RULE* parentRule;
DRC_CONSTRAINT constraint;
};
struct CONSTRAINT_SET
{
std::vector<CONSTRAINT_WITH_CONDITIONS*> sortedConstraints;
DRC_TEST_PROVIDER* provider;
DRC_TEST_PROVIDER* provider;
};
typedef std::unordered_map<test::DRC_CONSTRAINT_TYPE_T, CONSTRAINT_SET*> CONSTRAINT_MAP;
typedef std::unordered_map<DRC_CONSTRAINT_TYPE_T, CONSTRAINT_SET*> CONSTRAINT_MAP;
void inferLegacyRules();
void loadTestProviders();
test::DRC_RULE* createInferredRule( const wxString& name, std::set<BOARD_ITEM*> items, int priority );
DRC_RULE* createInferredRule( const wxString& name, std::set<BOARD_ITEM*> items, int priority );
BOARD_DESIGN_SETTINGS* m_designSettings;
BOARD* m_board;
KIGFX::WS_PROXY_VIEW_ITEM* m_worksheet;
NETLIST* m_schematicNetlist;
protected:
BOARD_DESIGN_SETTINGS* m_designSettings;
BOARD* m_board;
KIGFX::WS_PROXY_VIEW_ITEM* m_worksheet;
NETLIST* m_schematicNetlist;
std::shared_ptr<DRC_REPORT> m_drcReport;
std::shared_ptr<DRC_REPORT> m_drcReport;
std::vector<DRC_RULE_CONDITION*> m_ruleConditions;
std::vector<DRC_RULE*> m_rules;
std::vector<DRC_TEST_PROVIDER*> m_testProviders;
std::unordered_map<EDA_ITEM*, CONSTRAINT_SET*> m_implicitRules;
CONSTRAINT_MAP m_constraintMap;
REPORTER* m_reporter;
PROGRESS_REPORTER* m_progressReporter;
CONSTRAINT_MAP m_constraintMap;
REPORTER* m_reporter;
PROGRESS_REPORTER* m_progressReporter;
// condition -> rule -> provider
};
}; // namespace test
#endif // DRC_H
......@@ -79,6 +79,10 @@ DRC_ITEM DRC_ITEM::trackDangling( DRCE_DANGLING_TRACK,
_( "Track has unconnected end" ),
wxT( "track_dangling" ) );
DRC_ITEM DRC_ITEM::holeClearance( DRCE_HOLE_CLEARANCE,
_( "Hole clearance" ),
wxT( "hole_clearance" ) );
DRC_ITEM DRC_ITEM::holeNearHole( DRCE_DRILLED_HOLES_TOO_CLOSE,
_( "Drilled holes too close together" ),
wxT( "hole_near_hole" ) );
......@@ -91,9 +95,9 @@ DRC_ITEM DRC_ITEM::viaTooSmall( DRCE_TOO_SMALL_VIA,
_( "Via size too small" ),
wxT( "via_too_small" ) );
DRC_ITEM DRC_ITEM::viaAnnulus( DRCE_VIA_ANNULUS,
_( "Via annulus" ),
wxT( "via_annulus" ) );
DRC_ITEM DRC_ITEM::annulus( DRCE_ANNULUS,
_( "Annulus" ),
wxT( "annulus" ) );
DRC_ITEM DRC_ITEM::drillTooSmall( DRCE_TOO_SMALL_DRILL,
_( "Drill too small" ),
......@@ -180,9 +184,10 @@ std::vector<std::reference_wrapper<RC_ITEM>> DRC_ITEM::allItemTypes( {
DRC_ITEM::viaDangling,
DRC_ITEM::trackDangling,
DRC_ITEM::holeNearHole,
DRC_ITEM::holeClearance,
DRC_ITEM::trackWidth,
DRC_ITEM::viaTooSmall,
DRC_ITEM::viaAnnulus,
DRC_ITEM::annulus,
DRC_ITEM::drillTooSmall,
DRC_ITEM::viaHoleLargerThanPad,
DRC_ITEM::padstack,
......@@ -199,6 +204,7 @@ std::vector<std::reference_wrapper<RC_ITEM>> DRC_ITEM::allItemTypes( {
DRC_ITEM::duplicateFootprints,
DRC_ITEM::missingFootprint,
DRC_ITEM::extraFootprint,
DRC_ITEM::netConflict,
DRC_ITEM::unresolvedVariable
} );
......@@ -218,9 +224,10 @@ std::shared_ptr<DRC_ITEM> DRC_ITEM::Create( int aErrorCode )
case DRCE_DANGLING_VIA: return std::make_shared<DRC_ITEM>( viaDangling );
case DRCE_DANGLING_TRACK: return std::make_shared<DRC_ITEM>( trackDangling );
case DRCE_DRILLED_HOLES_TOO_CLOSE: return std::make_shared<DRC_ITEM>( holeNearHole );
case DRCE_HOLE_CLEARANCE: return std::make_shared<DRC_ITEM>( holeClearance );
case DRCE_TRACK_WIDTH: return std::make_shared<DRC_ITEM>( trackWidth );
case DRCE_TOO_SMALL_VIA: return std::make_shared<DRC_ITEM>( viaTooSmall );
case DRCE_VIA_ANNULUS: return std::make_shared<DRC_ITEM>( viaAnnulus );
case DRCE_ANNULUS: return std::make_shared<DRC_ITEM>( annulus );
case DRCE_TOO_SMALL_DRILL: return std::make_shared<DRC_ITEM>( drillTooSmall );
case DRCE_VIA_HOLE_BIGGER: return std::make_shared<DRC_ITEM>( viaHoleLargerThanPad );
case DRCE_PADSTACK: return std::make_shared<DRC_ITEM>( padstack );
......