Commit 1cae451b authored by Jonathan Klimt's avatar Jonathan Klimt

Initial commit

parents
[build]
# Pick ONE of these compilation targets
# target = "thumbv6m-none-eabi" # Cortex-M0 and Cortex-M0+
target = "thumbv7m-none-eabi" # Cortex-M3
# target = "thumbv7em-none-eabi" # Cortex-M4 and Cortex-M7 (no FPU)
# target = "thumbv7em-none-eabihf" # Cortex-M4F and Cortex-M7F (with FPU)
rustflags = [
# LLD (shipped with the Rust toolchain) is used as the default linker
"-C", "link-arg=-Tlink.x",
# if you run into problems with LLD switch to the GNU linker by commenting out
# this line
# "-C", "linker=arm-none-eabi-ld",
# if you need to link to pre-compiled C libraries provided by a C toolchain
# use GCC as the linker by commenting out both lines above and then
# uncommenting the three lines below
# "-C", "linker=arm-none-eabi-gcc",
# "-C", "link-arg=-Wl,-Tlink.x",
# "-C", "link-arg=-nostartfiles",
]
/target
**/*.rs.bk
*.bin
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[package]
name = "stm32_blink"
version = "0.1.0"
edition = "2018"
[profile.release]
# optimize for size ('z' would optimize even more)
opt-level = 's'
# link with link time optimization (lto).
lto = true
# enable debugging in release mode.
debug = true
[dependencies]
# Gives us access to the STM32F1 registers
stm32f1 = {version = "0.6.0", features = ["stm32f103", "rt"]}
# provides startup code for the ARM CPU
cortex-m-rt = "0.6.7"
# provides access to low level ARM CPU registers (used for delay)
cortex-m = "0.5.8"
# provies a panic-handler (halting cpu)
# (required when not using stdlib)
panic-halt = "0.2.0"
/* Linker script for the STM32F103C8T6 */
MEMORY
{
FLASH : ORIGIN = 0x08000000, LENGTH = 64K
RAM : ORIGIN = 0x20000000, LENGTH = 20K
}
// std and main are not available for bare metal software
#![no_std]
#![no_main]
extern crate stm32f1;
extern crate panic_halt;
extern crate cortex_m_rt;
use cortex_m_rt::entry;
use stm32f1::stm32f103;
// use `main` as the entry point of this application
#[entry]
fn main() -> ! {
// get handles to the hardware
let peripherals = stm32f103::Peripherals::take().unwrap();
let gpioc = &peripherals.GPIOC;
let rcc = &peripherals.RCC;
// enable the GPIO clock for IO port C
rcc.apb2enr.write(|w| w.iopcen().set_bit());
gpioc.crh.write(|w| unsafe{
w.mode13().bits(0b11);
w.cnf13().bits(0b00)
});
loop{
gpioc.bsrr.write(|w| w.bs13().set_bit());
cortex_m::asm::delay(2000000);
gpioc.brr.write(|w| w.br13().set_bit());
cortex_m::asm::delay(2000000);
}
}
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