Project/easy_dpp.md

@@ -99,9 +99,32 @@ when its value (derivative) esceeds a threshold values defined
 by the user in runtime and, stores the amplitude value in another
 FIFO (Comblock In) to be read afterwards.
 
+The DPP_0 block have the following Ports:
+
+| Port | Type | Definition |
+| ---- | ---- | ---------- |
+| clk_i | Input | Clock Input |
+| rst_i | Input | Reset Input |
+| ena_i | Input | DPP_0 Enable signal |
+| ADC_data_i | Input | Data Input |
+| threshold_high_i | Input | Detection Threshold value |
+| op_mode_i | Input | Operation Mode* |
+| data_o | Output | Data Output |
+| fir_wr_en_mux_out | Output | FIFO Write Enable/ Data Valid|
+
+The four operation modes are the following:
+
+| Operation Mode | Description |
+| -------------- | ----------- |
+| "00" | Amplitude acquisition |
+| "01" | Input signal |
+| "10" | Long FIR continuous output |
+| "11" | Derivative FIR continuous output |
+
 
 
 ## Procedure
+### Prepare the Project
 1. Generate the project in Vivado for the Zedboard using the information given in the previous section.
 2. Create a Block Design
 3. Include the Processing System
@@ -116,16 +139,10 @@ FIFO (Comblock In) to be read afterwards.
    
     Open the HDL files and try to understand its behavior.
 
-6. Insert the **DPP_module_top_0.vhd** in the block design, making right click on it and selecting the option `Add Module to the Block Design`
 
-    ![image2](../uploads/dpp0/img/include_bd.png)
+### Simulate the DPP to understand its behaviour.
 
-7. Once the DPP module is inserted in the bd, connect the signals as in the next figure:
-   ![easy_dpp_0](../uploads/Project/easy_dpp_0.png)
-
-   **Note:** Try to undesrtand the purpose of each connection. Can the design be simplified? 
-
-8. Generate a testbench/feeder for the DPP design
+6. Generate a testbench/feeder for the DPP design
     1. Add all the files under `<easy_dpp_git_path>/dpp_0/simul` to the **"Simulation sources"**. 
    
       ![sim_src_2](../uploads/dpp0/img/sim_src.png)
@@ -136,16 +153,38 @@ FIFO (Comblock In) to be read afterwards.
 
 
 
-    2. In the **"Project Manager"** make click on `Run Simulation -> Run Behavioral Simulation`
+    2. In the **"Project Manager"** make click on `Run Simulation -> Run Behavioral Simulation`.
+   
+    3. Run the Simulation for at least 10 uS. 
+        ![](../uploads/dpp0/img/Simulation.png)
+        **Note:** You can change the waveform style by **right clicking** the signal (e.g. data_in), and selecting the option `Waveform style -> Analog`, adjust your settings to improve the visualization in: `Waveform style -> Analog Settings` and change the **Interpolation style** to **Hold**.
+
+        ![](../uploads/dpp0/img/analog_settings.png)
 
-    3. Modify the DPP's parameters and see the change in the behaviour (op_mode_i, threshold_i, etc..)
+    4. Modify the DPP's parameters and see the change in the behaviour (op_mode_i, threshold_i, etc..).
 
-    4. Change the threshold values until you have only 5 pulses to be written in the FIFO.
 
-    5. Explore the different operation modes
-9.  Connect the signals of the DPP in the block design in order to be able to control it with the Comblock.
-10. Generate bitstream, export it and open the SDK
-11. Using the “hello world” template test the DPP feeding it through the Comblock’s FIFO and print the values of the pulses
+        ```--Input Parameters, Modify Here
+            ena <= '1';
+            threshold_high <= std_logic_vector(to_unsigned(80,16));
+            op_mode <="00";
+        ```
+          
+    5. Change the threshold values until you have only 5 pulses to be written in the FIFO (**Tip:** Check the *data_to_fifo* signal ).
+    6. Explore the different operation modes to understand their behaviour.
+
+### Create a Block Design project.
+7. Insert the **DPP_module_top_0.vhd** in the block design, making right click on it and selecting the option `Add Module to the Block Design`
+
+    ![image2](../uploads/dpp0/img/include_bd.png)
+
+8. Once the DPP module is inserted in the bd, connect the signals to a COMBLOCK, one example is given in the following figure:
+   ![easy_dpp_0](../uploads/Project/easy_dpp_0.png)
+
+   **Note:** Try to undesrtand the purpose of each connection. Can the design be simplified? 
+
+9.  **Generate Bitstream**, export it and create a Vitis project following the [overall project convetion](#Overal-Project-Information-and-Conventions). 
+10. Using the “hello world” template test the DPP feeding it through the Comblock’s FIFO and print the values of the pulses