@@ -123,7 +122,7 @@ The four operation modes are the following:
## Procedure
## DPP_0 Procedure
### Prepare the Project
1. Generate the project in Vivado for the Zedboard using the information given in the previous section.
2. Create a Block Design
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@@ -178,38 +177,76 @@ The four operation modes are the following:
8. Once the DPP module is inserted in the bd, connect the signals to a COMBLOCK, one example is given in the following figure:
8. Once the DPP module is inserted in the bd, connect the signals to a COMBLOCK as shown in the following figure:
**Note:** Try to undesrtand the purpose of each connection. Can the design be simplified?
9.**Generate Bitstream**, export it and create a Vitis project following the [overall project convetion](##Overal-Project-Information-and-Conventions).
9. **Generate Bitstream**, export it and create a **Vitis project** following the [overall project convetion](#overal-project-information-and-conventions).
10. Change the threshold and operation mode to obtain different outcomes.
# Digital Pulse Processor, Light version 1
In the previous section we got familiar with the concept of a DPP and the basic working principle of it.
This section will explore a more advanced one based on real data of the Electromanetic Calorimeter.
ECAL2 Pulses
This first version of the DPP is for processing pulses created
as the ECAL2 COMPASS detectors, the IP takes a stream of data
from a FIFO (Comblock FIFO Out), detects the arrival of a pulse
with a mean derivative and when its value (derivative) exceeds
ther threshold values defined by the user in runtime and, stores
the amplitude value in another FIFO (Comblock In) to be read
afterwards.
The DPP_0 block have the following Ports:
### Implementation in the Zedboard
1. Generate the output products and the bitstream
| Port | Type | Definition |
| ---- | ---- | ---------- |
| clk_i | Input | Clock Input |
| rst_i | Input | Reset Input |
| ena_i | Input | DPP_0 Enable signal |
| ADC_data_i | Input | Data Input |
|cf_1 | Input | FIR derivative coeficient 1 |
|cf_2 | Input | FIR derivative coeficient 2 |
|cf_3 | Input | FIR derivative coeficient 3 |
| threshold_high_i | Input | Detection Threshold of input over value |
| threshold_low_i | Input | Detection Threshold of input below value |
| op_mode_i | Input | Operation Mode* |
|delay_tap | Input | Delay counter |
| data_o | Output | Data Output |
| fir_wr_en_mux_out | Output | FIFO Write Enable/ Data Valid|
2. Export hardware
The four operation modes are the following:
3. Launch SDK
| Operation Mode | Description |
| -------------- | ----------- |
| "00" | Amplitude acquisition |
| "01" | Input signal |
| "10" | Long FIR continuous output |
| "11" | Derivative FIR continuous output |
4. Create application project, in standalone way for the "hello world"
## Procedure
5. Replace the **helloworld.c** with the one we provide in the **dpp_0/sdk** directory.
1. Follow the steps 1 to 5 from the [DPP_0 Procedure](#dpp_0-procedure) using the sources from `<easy_dpp_git_path>/dpp_1/src/`.
2. Import all the sources from `<easy_dpp_git_path>/dpp_1/simul/` and run a behavioural simulation for at least 10 uS.
4.**Generate Bitstream**, export it and create a **Vitis project** following the [overall project convetion](#overal-project-information-and-conventions).
5. Change the different registres and operation mode to obtain different outcomes.
# Project Ideas
1. Implement the programmable tap delay (This to control when the write enable should activate
the fifo writing) with a comblock resource
2. Implement a peak detector using only the derivative value
