Commit 6db26f43 authored by Mark Yue's avatar Mark Yue
Browse files

Synchronize codes for OnePlus Nord N100 Oxygen OS 10.5.1.BE83BA


Signed-off-by: default avatarMark Yue <mark.yue@oneplus.com>
Change-Id: I10a8bc75f002087615e62cfba96e324413283cd2
parent 3b6ad87d
......@@ -137,7 +137,7 @@ all.config
kernel/configs/android-*.cfg
# vendor device tree directories
arch/arm64/boot/dts/vendor/
#arch/arm64/boot/dts/vendor/
# Tech package directories
techpack/
#techpack/
......@@ -208,7 +208,7 @@ $(KERNEL_HEADERS_INSTALL): $(KERNEL_OUT)
# Creating a dtb.img once the kernel is compiled if TARGET_KERNEL_APPEND_DTB is set to be false
$(INSTALLED_DTBIMAGE_TARGET): $(TARGET_PREBUILT_INT_KERNEL)
cat $(KERNEL_OUT)/arch/$(KERNEL_ARCH)/boot/dts/vendor/qcom/*.dtb > $@
cat $(KERNEL_OUT)/arch/$(KERNEL_ARCH)/boot/dts/vendor/*/*.dtb > $@
.PHONY: kerneltags
kerneltags: $(KERNEL_OUT) $(KERNEL_CONFIG)
......
......@@ -418,6 +418,7 @@ LINUXINCLUDE := \
-I$(objtree)/arch/$(SRCARCH)/include/generated \
$(if $(KBUILD_SRC), -I$(srctree)/include) \
-I$(objtree)/include \
-I$(srctree)/drivers/oneplus/include \
$(USERINCLUDE)
KBUILD_AFLAGS := -D__ASSEMBLY__
......
......@@ -260,6 +260,9 @@ config ZONE_DMA32
config HAVE_GENERIC_GUP
def_bool y
config ONEPLUS_KEVENT_UPLOAD
def_bool y
config SMP
def_bool y
......
ifeq ($(CONFIG_BUILD_ARM64_DT_OVERLAY),y)
dtbo-$(CONFIG_ARCH_KONA) += \
kona-cdp-overlay.dtbo \
kona-cdp-lcd-overlay.dtbo \
kona-mtp-overlay.dtbo \
kona-mtp-ws-overlay.dtbo \
kona-xr-overlay.dtbo \
kona-rumi-overlay.dtbo \
kona-qrd-overlay.dtbo \
kona-hdk-overlay.dtbo
kona-cdp-overlay.dtbo-base := kona.dtb kona-v2.dtb kona-v2.1.dtb
kona-cdp-lcd-overlay.dtbo-base := kona.dtb kona-v2.dtb kona-v2.1.dtb
kona-mtp-overlay.dtbo-base := kona.dtb kona-v2.dtb kona-v2.1.dtb
kona-mtp-ws-overlay.dtbo-base := kona.dtb kona-v2.dtb kona-v2.1.dtb
kona-xr-overlay.dtbo-base := kona.dtb kona-v2.dtb kona-v2.1.dtb
kona-rumi-overlay.dtbo-base := kona.dtb kona-v2.dtb kona-v2.1.dtb
kona-qrd-overlay.dtbo-base := kona.dtb kona-v2.dtb kona-v2.1.dtb
kona-hdk-overlay.dtbo-base := kona.dtb kona-v2.dtb kona-v2.1.dtb
else
dtb-$(CONFIG_ARCH_KONA) += kona-rumi.dtb \
kona-mtp.dtb \
kona-mtp-ws.dtb \
kona-xr.dtb \
kona-cdp.dtb \
kona-cdp-lcd.dtb \
kona-qrd.dtb \
kona-v2-rumi.dtb \
kona-v2-mtp.dtb \
kona-v2-mtp-ws.dtb \
kona-v2-cdp.dtb \
kona-v2-qrd.dtb \
kona-hdk.dtb \
kona-v2.1-mtp.dtb \
kona-v2.1-mtp-ws.dtb \
kona-v2.1-cdp.dtb \
kona-v2.1-qrd.dtb \
kona-v2.1-hdk.dtb \
kona-v2.1-iot-rb5.dtb
endif
ifeq ($(CONFIG_BUILD_ARM64_DT_OVERLAY),y)
dtbo-$(CONFIG_ARCH_LITO) += lito-rumi-overlay.dtbo \
lito-mtp-overlay.dtbo \
lito-v2-mtp-overlay.dtbo \
lito-cdp-overlay.dtbo \
lito-v2-cdp-overlay.dtbo \
lito-atp-overlay.dtbo \
lito-v2-atp-overlay.dtbo \
lito-qrd-overlay.dtbo \
lito-v2-qrd-overlay.dtbo
lito-rumi-overlay.dtbo-base := lito.dtb lito-v2.dtb
lito-mtp-overlay.dtbo-base := lito.dtb
lito-v2-mtp-overlay.dtbo-base := lito-v2.dtb
lito-cdp-overlay.dtbo-base := lito.dtb
lito-v2-cdp-overlay.dtbo-base := lito-v2.dtb
lito-atp-overlay.dtbo-base := lito.dtb
lito-v2-atp-overlay.dtbo-base := lito-v2.dtb
lito-qrd-overlay.dtbo-base := lito.dtb
lito-v2-qrd-overlay.dtbo-base := lito-v2.dtb
else
dtb-$(CONFIG_ARCH_LITO) += lito-rumi.dtb \
lito-mtp.dtb \
lito-cdp.dtb \
lito-atp.dtb \
lito-qrd.dtb \
lito-v2-mtp.dtb \
lito-v2-cdp.dtb \
lito-v2-atp.dtb \
lito-v2-qrd.dtb
endif
ifeq ($(CONFIG_BUILD_ARM64_DT_OVERLAY),y)
dtbo-$(CONFIG_ARCH_LAGOON) += \
lagoon-rumi-overlay.dtbo \
lagoon-mtp-overlay.dtbo \
lagoon-mtp-usbc-overlay.dtbo \
lagoon-cdp-overlay.dtbo \
lagoon-atp-overlay.dtbo \
lagoon-qrd-overlay.dtbo
lagoon-rumi-overlay.dtbo-base := lagoon.dtb
lagoon-mtp-overlay.dtbo-base := lagoon.dtb
lagoon-mtp-usbc-overlay.dtbo-base := lagoon.dtb
lagoon-cdp-overlay.dtbo-base := lagoon.dtb
lagoon-atp-overlay.dtbo-base := lagoon.dtb
lagoon-qrd-overlay.dtbo-base := lagoon.dtb
else
dtb-$(CONFIG_ARCH_LAGOON) += \
lagoon-rumi.dtb \
lagoon-mtp.dtb \
lagoon-mtp-usbc.dtb \
lagoon-cdp.dtb \
lagoon-atp.dtb \
lagoon-qrd.dtb
endif
ifeq ($(CONFIG_BUILD_ARM64_DT_OVERLAY),y)
dtbo-$(CONFIG_ARCH_BENGAL) += \
bengal-rumi-overlay.dtbo \
bengal-qrd-overlay.dtbo \
bengal-idp-overlay.dtbo \
bengal-idp-usbc-overlay.dtbo \
bengalp-idp-overlay.dtbo \
bengal-idp-1gb-overlay.dtbo \
bengal-idp-2gb-overlay.dtbo \
bengal-idp-usbc-1gb-overlay.dtbo \
bengal-idp-usbc-2gb-overlay.dtbo
bengal-rumi-overlay.dtbo-base := bengal.dtb
bengal-qrd-overlay.dtbo-base := bengal.dtb
bengal-idp-overlay.dtbo-base := bengal.dtb
bengal-idp-usbc-overlay.dtbo-base := bengal.dtb
bengalp-idp-overlay.dtbo-base := bengalp.dtb
bengal-idp-1gb-overlay.dtbo-base := bengal-1gb.dtb
bengal-idp-2gb-overlay.dtbo-base := bengal-2gb.dtb
bengal-idp-usbc-1gb-overlay.dtbo-base := bengal-1gb.dtb
bengal-idp-usbc-2gb-overlay.dtbo-base := bengal-2gb.dtb
else
dtb-$(CONFIG_ARCH_BENGAL) += bengal-rumi.dtb \
bengal-qrd.dtb \
bengal-idp.dtb \
bengal-idp-usbc.dtb \
bengalp-idp.dtb \
bengal-idp-1gb.dtb \
bengal-idp-2gb.dtb \
bengal-idp-usbc-1gb.dtb \
bengal-idp-usbc-2gb.dtb
endif
ifeq ($(CONFIG_BUILD_ARM64_DT_OVERLAY),y)
dtbo-$(CONFIG_ARCH_SCUBA) += \
scuba-rumi-overlay.dtbo \
scuba-idp-overlay.dtbo \
scuba-qrd-overlay.dtbo
scuba-rumi-overlay.dtbo-base := scuba.dtb
scuba-idp-overlay.dtbo-base := scuba.dtb
scuba-qrd-overlay.dtbo-base := scuba.dtb
else
dtb-$(CONFIG_ARCH_SCUBA) += scuba-rumi.dtb \
scuba-idp.dtb \
scuba-qrd.dtb
endif
always := $(dtb-y)
subdir-y := $(dts-dirs)
clean-files := *.dtb *.dtbo
/dts-v1/;
#include "bengal-low-ram.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Bengal 1Gb DDR HD+ SoC";
compatible = "qcom,bengal";
qcom,board-id = <0 0x303>;
};
/dts-v1/;
#include "bengal-low-ram.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Bengal 2Gb DDR HD+ SoC";
compatible = "qcom,bengal";
qcom,board-id = <0 0x403>;
};
#include <dt-bindings/clock/qcom,audio-ext-clk.h>
#include <dt-bindings/sound/qcom,bolero-clk-rsc.h>
#include <dt-bindings/sound/audio-codec-port-types.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include "bengal-lpi.dtsi"
#include "bengal-sia81xx.dtsi"
&bolero {
qcom,num-macros = <3>;
qcom,bolero-version = <5>;
bolero-clk-rsc-mngr {
compatible = "qcom,bolero-clk-rsc-mngr";
qcom,fs-gen-sequence = <0x3000 0x1>,
<0x3004 0x1>, <0x3080 0x2>;
qcom,rx_mclk_mode_muxsel = <0x0a5640d8>;
qcom,va_mclk_mode_muxsel = <0x0a7a0000>;
clock-names = "tx_core_clk", "tx_npl_clk", "rx_core_clk", "rx_npl_clk",
"va_core_clk", "va_npl_clk";
clocks = <&clock_audio_tx_1 0>, <&clock_audio_tx_2 0>,
<&clock_audio_rx_1 0>, <&clock_audio_rx_2 0>,
<&clock_audio_va_1 0>, <&clock_audio_va_2 0>;
};
tx_macro: tx-macro@a620000 {
compatible = "qcom,tx-macro";
reg = <0xa620000 0x0>;
clock-names = "tx_core_clk", "tx_npl_clk";
clocks = <&clock_audio_tx_1 0>,
<&clock_audio_tx_2 0>;
qcom,tx-dmic-sample-rate = <2400000>;
qcom,is-used-swr-gpio = <0>;
};
rx_macro: rx-macro@a600000 {
compatible = "qcom,rx-macro";
reg = <0xa600000 0x0>;
clock-names = "rx_core_clk", "rx_npl_clk";
clocks = <&clock_audio_rx_1 0>,
<&clock_audio_rx_2 0>;
qcom,rx-swr-gpios = <&rx_swr_gpios>;
qcom,rx_mclk_mode_muxsel = <0x0a5640d8>;
qcom,rx-bcl-pmic-params = /bits/ 8 <0x00 0x04 0x3E>;
qcom,default-clk-id = <TX_CORE_CLK>;
swr1: rx_swr_master {
compatible = "qcom,swr-mstr";
#address-cells = <2>;
#size-cells = <0>;
clock-names = "lpass_audio_hw_vote";
clocks = <&lpass_audio_hw_vote 0>;
qcom,swr_master_id = <2>;
qcom,swrm-hctl-reg = <0x0a6a9098>;
qcom,mipi-sdw-block-packing-mode = <1>;
swrm-io-base = <0xa610000 0x0>;
interrupts = <0 297 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "swr_master_irq";
qcom,swr-num-ports = <5>;
qcom,swr-port-mapping = <1 HPH_L 0x1>,
<1 HPH_R 0x2>, <2 CLSH 0x1>,
<3 COMP_L 0x1>, <3 COMP_R 0x2>,
<4 LO 0x1>, <5 DSD_L 0x1>,
<5 DSD_R 0x2>;
qcom,swr-num-dev = <1>;
qcom,swr-clock-stop-mode0 = <1>;
wcd937x_rx_slave: wcd937x-rx-slave {
compatible = "qcom,wcd937x-slave";
reg = <0x0A 0x01170224>;
};
};
};
va_macro: va-macro@a730000 {
compatible = "qcom,va-macro";
reg = <0xa730000 0x0>;
clock-names = "lpass_audio_hw_vote";
clocks = <&lpass_audio_hw_vote 0>;
qcom,va-dmic-sample-rate = <600000>;
qcom,va-clk-mux-select = <1>;
qcom,va-island-mode-muxsel = <0x0a7a0000>;
qcom,default-clk-id = <TX_CORE_CLK>;
qcom,is-used-swr-gpio = <1>;
qcom,va-swr-gpios = <&va_swr_gpios>;
swr0: va_swr_master {
compatible = "qcom,swr-mstr";
#address-cells = <2>;
#size-cells = <0>;
clock-names = "lpass_audio_hw_vote";
clocks = <&lpass_audio_hw_vote 0>;
qcom,swr_master_id = <3>;
qcom,swrm-hctl-reg = <0x0a7ec100>;
qcom,mipi-sdw-block-packing-mode = <1>;
swrm-io-base = <0xa740000 0x0>;
interrupts =
<0 296 IRQ_TYPE_LEVEL_HIGH>,
<0 79 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "swr_master_irq", "swr_wake_irq";
qcom,swr-wakeup-required = <1>;
qcom,swr-num-ports = <3>;
qcom,swr-port-mapping = <1 ADC1 0x1>, <1 ADC2 0x2>,
<1 ADC3 0x4>, <1 ADC4 0x8>,
<2 DMIC0 0x1>, <2 DMIC1 0x2>,
<2 DMIC2 0x4>, <2 DMIC3 0x8>,
<3 DMIC4 0x1>, <3 DMIC5 0x2>,
<3 DMIC6 0x4>, <3 DMIC7 0x8>;
qcom,swr-num-dev = <1>;
qcom,swr-clock-stop-mode0 = <1>;
qcom,swr-mstr-irq-wakeup-capable = <1>;
wcd937x_tx_slave: wcd937x-tx-slave {
compatible = "qcom,wcd937x-slave";
reg = <0x0A 0x01170223>;
};
};
};
wcd937x_codec: wcd937x-codec {
compatible = "qcom,wcd937x-codec";
qcom,split-codec = <1>;
qcom,rx_swr_ch_map = <0 HPH_L 0x1 0 HPH_L>,
<0 HPH_R 0x2 0 HPH_R>, <1 CLSH 0x1 0 CLSH>,
<2 COMP_L 0x1 0 COMP_L>, <2 COMP_R 0x2 0 COMP_R>,
<3 LO 0x1 0 LO>, <4 DSD_L 0x1 0 DSD_L>,
<4 DSD_R 0x2 0 DSD_R>;
qcom,tx_swr_ch_map = <0 ADC1 0x1 0 ADC1>,
<1 ADC2 0x1 0 DMIC0>, <1 ADC3 0x2 0 DMIC1>,
<2 DMIC0 0x1 0 DMIC4>, <2 DMIC1 0x2 0 DMIC5>,
<2 MBHC 0x4 0 DMIC6>, <3 DMIC2 0x1 0 DMIC4>,
<3 DMIC3 0x2 0 DMIC5>, <3 DMIC4 0x4 0 DMIC6>,
<3 DMIC5 0x8 0 DMIC7>;
qcom,wcd-rst-gpio-node = <&wcd937x_rst_gpio>;
qcom,rx-slave = <&wcd937x_rx_slave>;
qcom,tx-slave = <&wcd937x_tx_slave>;
cdc-vdd-rxtx-supply = <&L9A>;
qcom,cdc-vdd-rxtx-voltage = <1800000 1800000>;
qcom,cdc-vdd-rxtx-current = <10000>;
cdc-vddpx-supply = <&L9A>;
qcom,cdc-vddpx-voltage = <1800000 1800000>;
qcom,cdc-vddpx-current = <20000>;
cdc-vdd-buck-supply = <&L14A>;
qcom,cdc-vdd-buck-voltage = <1800000 1800000>;
qcom,cdc-vdd-buck-current = <650000>;
qcom,cdc-micbias1-mv = <1800>;
qcom,cdc-micbias2-mv = <2700>;
qcom,cdc-micbias3-mv = <1800>;
qcom,cdc-static-supplies = "cdc-vdd-rxtx",
"cdc-vddpx";
qcom,cdc-on-demand-supplies = "cdc-vdd-buck";
};
};
&bengal_snd {
qcom,model = "bengal-idp-snd-card";
qcom,msm-mi2s-master = <1>, <1>, <1>, <1>;
qcom,wcn-btfm = <1>;
qcom,va-bolero-codec = <1>;
qcom,rxtx-bolero-codec = <1>;
qcom,audio-routing =
"AMIC1", "MIC BIAS1",
"MIC BIAS1", "Analog Mic1",
"AMIC2", "MIC BIAS2",
"MIC BIAS2", "Analog Mic2",
"AMIC3", "MIC BIAS3",
"MIC BIAS3", "Analog Mic3",
"AMIC4", "MIC BIAS3",
"MIC BIAS3", "Analog Mic4",
"TX DMIC0", "MIC BIAS1",
"MIC BIAS1", "Digital Mic0",
"TX DMIC1", "MIC BIAS1",
"MIC BIAS1", "Digital Mic1",
"TX DMIC2", "MIC BIAS3",
"MIC BIAS3", "Digital Mic2",
"TX DMIC3", "MIC BIAS3",
"MIC BIAS3", "Digital Mic3",
"IN1_HPHL", "HPHL_OUT",
"IN2_HPHR", "HPHR_OUT",
"IN3_AUX", "AUX_OUT",
"SpkrMono WSA_IN", "AUX",
"TX SWR_MIC0", "ADC1_OUTPUT",
"TX SWR_MIC4", "ADC2_OUTPUT",
"TX SWR_MIC5", "ADC3_OUTPUT",
"TX SWR_MIC8", "DMIC1_OUTPUT",
"TX SWR_MIC9", "DMIC2_OUTPUT",
"TX SWR_MIC8", "DMIC3_OUTPUT",
"TX SWR_MIC9", "DMIC4_OUTPUT",
"TX SWR_MIC10", "DMIC5_OUTPUT",
"TX SWR_MIC11", "DMIC6_OUTPUT",
"TX SWR_MIC0", "VA_TX_SWR_CLK",
"TX SWR_MIC1", "VA_TX_SWR_CLK",
"TX SWR_MIC2", "VA_TX_SWR_CLK",
"TX SWR_MIC3", "VA_TX_SWR_CLK",
"TX SWR_MIC4", "VA_TX_SWR_CLK",
"TX SWR_MIC5", "VA_TX_SWR_CLK",
"TX SWR_MIC6", "VA_TX_SWR_CLK",
"TX SWR_MIC7", "VA_TX_SWR_CLK",
"TX SWR_MIC8", "VA_TX_SWR_CLK",
"TX SWR_MIC9", "VA_TX_SWR_CLK",
"TX SWR_MIC10", "VA_TX_SWR_CLK",
"TX SWR_MIC11", "VA_TX_SWR_CLK",
"RX_TX DEC0_INP", "TX DEC0 MUX",
"RX_TX DEC1_INP", "TX DEC1 MUX",
"RX_TX DEC2_INP", "TX DEC2 MUX",
"RX_TX DEC3_INP", "TX DEC3 MUX",
"TX_AIF1 CAP", "VA_TX_SWR_CLK",
"TX_AIF2 CAP", "VA_TX_SWR_CLK",
"TX_AIF3 CAP", "VA_TX_SWR_CLK",
"VA DMIC0", "VA MIC BIAS1",
"VA DMIC1", "VA MIC BIAS1",
"VA DMIC2", "VA MIC BIAS3",
"VA DMIC3", "VA MIC BIAS3",
"VA MIC BIAS1", "Digital Mic0",
"VA MIC BIAS1", "Digital Mic1",
"VA MIC BIAS3", "Digital Mic2",
"VA MIC BIAS3", "Digital Mic3",
"VA SWR_MIC0", "ADC1_OUTPUT",
"VA SWR_MIC4", "ADC2_OUTPUT",
"VA SWR_MIC5", "ADC3_OUTPUT",
"VA SWR_MIC8", "DMIC1_OUTPUT",
"VA SWR_MIC9", "DMIC2_OUTPUT",
"VA SWR_MIC8", "DMIC3_OUTPUT",
"VA SWR_MIC9", "DMIC4_OUTPUT",
"VA SWR_MIC10", "DMIC5_OUTPUT",
"VA SWR_MIC11", "DMIC6_OUTPUT";
qcom,msm-mbhc-hphl-swh = <1>;
qcom,msm-mbhc-gnd-swh = <1>;
qcom,cdc-dmic01-gpios = <&cdc_dmic01_gpios>;
qcom,cdc-dmic23-gpios = <&cdc_dmic23_gpios>;
nvmem-cells = <&adsp_variant>;
nvmem-cell-names = "adsp_variant";
asoc-codec = <&stub_codec>, <&bolero>;
asoc-codec-names = "msm-stub-codec.1", "bolero_codec";
qcom,wsa-max-devs = <0>;
qcom,wsa-devs = <0>;
qcom,wsa-aux-dev-prefix = "SpkrMono";
qcom,codec-max-aux-devs = <1>;
qcom,codec-aux-devs = <&wcd937x_codec>;
qcom,msm_audio_ssr_devs = <&audio_apr>, <&q6core>, <&bolero>,
<&lpi_tlmm>;
};
&qupv3_se1_i2c {
wsa881x_i2c_e: wsa881x-i2c-codec@e {
status = "disabled";
compatible = "qcom,wsa881x-i2c-codec";
reg = <0x0e>;
clock-names = "wsa_mclk";
clocks = <&wsa881x_analog_clk 0>;
qcom,wsa-analog-clk-gpio = <&wsa881x_analog_clk_gpio>;
qcom,wsa-analog-reset-gpio = <&wsa881x_analog_reset_gpio>;
};
wsa881x_i2c_44: wsa881x-i2c-codec@44 {
status = "disabled";
compatible = "qcom,wsa881x-i2c-codec";
reg = <0x044>;
};
};
&qupv3_se2_i2c {
aw87359@59 {
compatible = "awinic,aw87359_pa";
reg = <0x59>;
};
aw87529_pa@58 {
compatible = "awinic,aw87529_pa";
reg = <0x58>;
reset-gpio = <&tlmm 96 0>;
};
};
&q6core {
cdc_dmic01_gpios: cdc_dmic01_pinctrl {
compatible = "qcom,msm-cdc-pinctrl";
pinctrl-names = "aud_active", "aud_sleep";
pinctrl-0 = <&cdc_dmic01_clk_active &cdc_dmic01_data_active>;
pinctrl-1 = <&cdc_dmic01_clk_sleep &cdc_dmic01_data_sleep>;
qcom,lpi-gpios;
};
cdc_dmic23_gpios: cdc_dmic23_pinctrl {
compatible = "qcom,msm-cdc-pinctrl";
pinctrl-names = "aud_active", "aud_sleep";
pinctrl-0 = <&cdc_dmic23_clk_active &cdc_dmic23_data_active>;
pinctrl-1 = <&cdc_dmic23_clk_sleep &cdc_dmic23_data_sleep>;
qcom,lpi-gpios;
};
rx_swr_gpios: rx_swr_clk_data_pinctrl {
compatible = "qcom,msm-cdc-pinctrl";
pinctrl-names = "aud_active", "aud_sleep";
pinctrl-0 = <&rx_swr_clk_active &rx_swr_data_active
&rx_swr_data1_active>;
pinctrl-1 = <&rx_swr_clk_sleep &rx_swr_data_sleep
&rx_swr_data1_sleep>;
qcom,lpi-gpios;
};
va_swr_gpios: va_swr_clk_data_pinctrl {
compatible = "qcom,msm-cdc-pinctrl";
pinctrl-names = "aud_active", "aud_sleep";
pinctrl-0 = <&tx_swr_clk_active &tx_swr_data1_active
&tx_swr_data2_active>;
pinctrl-1 = <&tx_swr_clk_sleep &tx_swr_data1_sleep
&tx_swr_data2_sleep>;
qcom,lpi-gpios;
qcom,chip-wakeup-reg = <0x003ca04c>;
qcom,chip-wakeup-maskbit = <0>;
qcom,chip-wakeup-default-val = <0x1>;
};
};
&soc {
wcd937x_rst_gpio: msm_cdc_pinctrl@92 {
compatible = "qcom,msm-cdc-pinctrl";
pinctrl-names = "aud_active", "aud_sleep";
pinctrl-0 = <&wcd937x_reset_active>;
pinctrl-1 = <&wcd937x_reset_sleep>;
};
wsa881x_analog_reset_gpio: msm_cdc_pinctrl@106 {
compatible = "qcom,msm-cdc-pinctrl";
pinctrl-names = "aud_active", "aud_sleep";
pinctrl-0 = <&spkr_1_sd_n_active>;
pinctrl-1 = <&spkr_1_sd_n_sleep>;
};
wsa881x_analog_clk_gpio: msm_cdc_pinctrl@18 {
compatible = "qcom,msm-cdc-pinctrl";
pinctrl-names = "aud_active", "aud_sleep";
pinctrl-0 = <&wsa_mclk_active>;
pinctrl-1 = <&wsa_mclk_sleep>;
};
wsa881x_analog_clk: wsa_ana_clk {
compatible = "qcom,audio-ref-clk";
qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK_2>;
qcom,codec-lpass-ext-clk-freq = <9600000>;
qcom,codec-lpass-clk-id = <0x301>;
#clock-cells = <1>;
};
clock_audio_rx_1: rx_core_clk {
compatible = "qcom,audio-ref-clk";
qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK_4>;
qcom,codec-lpass-ext-clk-freq = <22579200>;
qcom,codec-lpass-clk-id = <0x30E>;
#clock-cells = <1>;
};
clock_audio_rx_2: rx_npl_clk {
compatible = "qcom,audio-ref-clk";
qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK_5>;
qcom,codec-lpass-ext-clk-freq = <22579200>;
qcom,codec-lpass-clk-id = <0x30F>;
#clock-cells = <1>;
};
clock_audio_tx_1: tx_core_clk {
compatible = "qcom,audio-ref-clk";
qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK_6>;
qcom,codec-lpass-ext-clk-freq = <19200000>;
qcom,codec-lpass-clk-id = <0x30C>;
#clock-cells = <1>;
};
clock_audio_tx_2: tx_npl_clk {
compatible = "qcom,audio-ref-clk";
qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK_7>;
qcom,codec-lpass-ext-clk-freq = <19200000>;
qcom,codec-lpass-clk-id = <0x30D>;
#clock-cells = <1>;
};
clock_audio_va_1: va_core_clk {
compatible = "qcom,audio-ref-clk";
qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK>;
qcom,codec-lpass-ext-clk-freq = <19200000>;
qcom,codec-lpass-clk-id = <0x30B>;
#clock-cells = <1>;
};
clock_audio_va_2: va_npl_clk {
compatible = "qcom,audio-ref-clk";
qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK_8>;
qcom,codec-lpass-ext-clk-freq = <19200000>;
qcom,codec-lpass-clk-id = <0x310>;
#clock-cells = <1>;
};
};
&va_cdc_dma_0_tx {
qcom,msm-dai-is-island-supported = <1>;
};
&adsp_loader {
nvmem-cells = <&adsp_variant>;
nvmem-cell-names = "adsp_variant";
adsp-fw-names = "adsp2";
adsp-fw-bit-values = <0x1>;