Commit a91a4cf8 authored by Iskren Chernev's avatar Iskren Chernev
Browse files

clk: qcom: smd: Add support for SM6115 rpm clocks



Add rpm smd clocks, PMIC and bus clocks which are required on
SM4250/SM6115 for clients to vote on.
Signed-off-by: default avatarIskren Chernev <iskren.chernev@gmail.com>
parent e3223ff9
......@@ -1059,6 +1059,68 @@ static const struct rpm_smd_clk_desc rpm_clk_sdm660 = {
.num_clks = ARRAY_SIZE(sdm660_clks),
};
/* sm6115 */
DEFINE_CLK_SMD_RPM_BRANCH(sm6115, bi_tcxo, bi_tcxo_ao,
QCOM_SMD_RPM_MISC_CLK, 0, 19200000);
DEFINE_CLK_SMD_RPM(sm6115, cnoc_clk, cnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 1);
DEFINE_CLK_SMD_RPM(sm6115, bimc_clk, bimc_a_clk, QCOM_SMD_RPM_MEM_CLK, 0);
DEFINE_CLK_SMD_RPM(sm6115, snoc_clk, snoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 2);
DEFINE_CLK_SMD_RPM_BRANCH(sm6115, qdss_clk, qdss_a_clk,
QCOM_SMD_RPM_MISC_CLK, 1, 19200000);
DEFINE_CLK_SMD_RPM(sm6115, ce1_clk, ce1_a_clk, QCOM_SMD_RPM_CE_CLK, 0);
DEFINE_CLK_SMD_RPM(sm6115, ipa_clk, ipa_a_clk, QCOM_SMD_RPM_IPA_CLK, 0);
DEFINE_CLK_SMD_RPM(sm6115, qup_clk, qup_a_clk, QCOM_SMD_RPM_QUP_CLK, 0);
DEFINE_CLK_SMD_RPM(sm6115, mmnrt_clk, mmnrt_a_clk, QCOM_SMD_RPM_MMAXI_CLK, 0);
DEFINE_CLK_SMD_RPM(sm6115, mmrt_clk, mmrt_a_clk, QCOM_SMD_RPM_MMAXI_CLK, 1);
DEFINE_CLK_SMD_RPM(sm6115, snoc_periph_clk, snoc_periph_a_clk,
QCOM_SMD_RPM_BUS_CLK, 0);
DEFINE_CLK_SMD_RPM(sm6115, snoc_lpass_clk, snoc_lpass_a_clk,
QCOM_SMD_RPM_BUS_CLK, 5);
DEFINE_CLK_SMD_RPM_XO_BUFFER(sm6115, rf_clk1, rf_clk1_a, 4);
DEFINE_CLK_SMD_RPM_XO_BUFFER(sm6115, rf_clk2, rf_clk2_a, 5);
DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(sm6115, rf_clk1_pin, rf_clk1_a_pin, 4);
DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(sm6115, rf_clk2_pin, rf_clk2_a_pin, 5);
static struct clk_smd_rpm *sm6115_clks[] = {
[RPM_SMD_XO_CLK_SRC] = &sm6115_bi_tcxo,
[RPM_SMD_XO_A_CLK_SRC] = &sm6115_bi_tcxo_ao,
[RPM_SMD_SNOC_CLK] = &sm6115_snoc_clk,
[RPM_SMD_SNOC_A_CLK] = &sm6115_snoc_a_clk,
[RPM_SMD_BIMC_CLK] = &sm6115_bimc_clk,
[RPM_SMD_BIMC_A_CLK] = &sm6115_bimc_a_clk,
[RPM_SMD_QDSS_CLK] = &sm6115_qdss_clk,
[RPM_SMD_QDSS_A_CLK] = &sm6115_qdss_a_clk,
[RPM_SMD_RF_CLK1] = &sm6115_rf_clk1,
[RPM_SMD_RF_CLK1_A] = &sm6115_rf_clk1_a,
[RPM_SMD_RF_CLK2] = &sm6115_rf_clk2,
[RPM_SMD_RF_CLK2_A] = &sm6115_rf_clk2_a,
[RPM_SMD_CNOC_CLK] = &sm6115_cnoc_clk,
[RPM_SMD_CNOC_A_CLK] = &sm6115_cnoc_a_clk,
[RPM_SMD_IPA_CLK] = &sm6115_ipa_clk,
[RPM_SMD_IPA_A_CLK] = &sm6115_ipa_a_clk,
[RPM_SMD_QUP_CLK] = &sm6115_qup_clk,
[RPM_SMD_QUP_A_CLK] = &sm6115_qup_a_clk,
[RPM_SMD_MMRT_CLK] = &sm6115_mmrt_clk,
[RPM_SMD_MMRT_A_CLK] = &sm6115_mmrt_a_clk,
[RPM_SMD_MMNRT_CLK] = &sm6115_mmnrt_clk,
[RPM_SMD_MMNRT_A_CLK] = &sm6115_mmnrt_a_clk,
[RPM_SMD_SNOC_PERIPH_CLK] = &sm6115_snoc_periph_clk,
[RPM_SMD_SNOC_PERIPH_A_CLK] = &sm6115_snoc_periph_a_clk,
[RPM_SMD_SNOC_LPASS_CLK] = &sm6115_snoc_lpass_clk,
[RPM_SMD_SNOC_LPASS_A_CLK] = &sm6115_snoc_lpass_a_clk,
[RPM_SMD_CE1_CLK] = &sm6115_ce1_clk,
[RPM_SMD_CE1_A_CLK] = &sm6115_ce1_a_clk,
[RPM_SMD_RF_CLK1_PIN] = &sm6115_rf_clk1_pin,
[RPM_SMD_RF_CLK1_A_PIN] = &sm6115_rf_clk1_a_pin,
[RPM_SMD_RF_CLK2_PIN] = &sm6115_rf_clk2_pin,
[RPM_SMD_RF_CLK2_A_PIN] = &sm6115_rf_clk2_a_pin,
};
static const struct rpm_smd_clk_desc rpm_clk_sm6115 = {
.clks = sm6115_clks,
.num_clks = ARRAY_SIZE(sm6115_clks),
};
static const struct of_device_id rpm_smd_clk_match_table[] = {
{ .compatible = "qcom,rpmcc-msm8916", .data = &rpm_clk_msm8916 },
{ .compatible = "qcom,rpmcc-msm8936", .data = &rpm_clk_msm8936 },
......@@ -1070,6 +1132,8 @@ static const struct of_device_id rpm_smd_clk_match_table[] = {
{ .compatible = "qcom,rpmcc-msm8998", .data = &rpm_clk_msm8998 },
{ .compatible = "qcom,rpmcc-qcs404", .data = &rpm_clk_qcs404 },
{ .compatible = "qcom,rpmcc-sdm660", .data = &rpm_clk_sdm660 },
{ .compatible = "qcom,rpmcc-sm4250", .data = &rpm_clk_sm6115 },
{ .compatible = "qcom,rpmcc-sm6115", .data = &rpm_clk_sm6115 },
{ }
};
MODULE_DEVICE_TABLE(of, rpm_smd_clk_match_table);
......
......@@ -241,6 +241,8 @@ static const struct of_device_id qcom_smd_rpm_of_match[] = {
{ .compatible = "qcom,rpm-msm8996" },
{ .compatible = "qcom,rpm-msm8998" },
{ .compatible = "qcom,rpm-sdm660" },
{ .compatible = "qcom,rpm-sm4250" },
{ .compatible = "qcom,rpm-sm6115" },
{ .compatible = "qcom,rpm-qcs404" },
{}
};
......
......@@ -149,5 +149,15 @@
#define RPM_SMD_CE2_A_CLK 103
#define RPM_SMD_CE3_CLK 104
#define RPM_SMD_CE3_A_CLK 105
#define RPM_SMD_QUP_CLK 106
#define RPM_SMD_QUP_A_CLK 107
#define RPM_SMD_MMRT_CLK 108
#define RPM_SMD_MMRT_A_CLK 109
#define RPM_SMD_MMNRT_CLK 110
#define RPM_SMD_MMNRT_A_CLK 111
#define RPM_SMD_SNOC_PERIPH_CLK 112
#define RPM_SMD_SNOC_PERIPH_A_CLK 113
#define RPM_SMD_SNOC_LPASS_CLK 114
#define RPM_SMD_SNOC_LPASS_A_CLK 115
#endif
......@@ -37,6 +37,7 @@ struct qcom_smd_rpm;
#define QCOM_SMD_RPM_IPA_CLK 0x617069
#define QCOM_SMD_RPM_CE_CLK 0x6563
#define QCOM_SMD_RPM_AGGR_CLK 0x72676761
#define QCOM_SMD_RPM_QUP_CLK 0x00707571
int qcom_rpm_smd_write(struct qcom_smd_rpm *rpm,
int state,
......
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