Tom Rini authored Nov 10, 2015 and Thomas Huth committed Oct 09, 2021

In 522b021a

 we dropped 'PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4)' lines in
the mpc85xx linker scripts as this is not required and breaks newer
binutils.  This commit cleans up the rest of the powerpc linker scripts.

Signed-off-by: Tom Rini <trini@konsulko.com>
(cherry picked from commit 7ff15aca)

Mans Rullgard authored Nov 06, 2015 and Thomas Huth committed Oct 09, 2021

A number of headers define functions as "extern inline" which is
causing problems with gcc5.  The reason is that starting with
version 5.1, gcc defaults to the standard C99 semantics for the
inline keyword.

Under the traditional GNU inline semantics, an "extern inline"
function would never create an external definition, the same
as inline *without* extern in C99.  In C99, and "extern inline"
definition is simply an external definition with an inline hint.
In short, the meanings of inline with and without extern are
swapped between GNU and C99.

The upshot is that all these definitions in header files create
an external definition wherever those headers are included,
resulting in multiple definition errors at link time.

Changing all these functions to "static inline" fixes the problem
since this works as desired in all gcc versions.  Although the
semantics are slightly different (a static inline definition may
result in an actual function being emitted), it works as intended
in practice.

This patch also removes extern prototype declarations for the
changed functions where they existed.

Signed-off-by: Mans Rullgard <mans@mansr.com>
(cherry picked from commit 44d0677a)

Signed-off-by: Tom Rini <trini@konsulko.com>

Simon Glass authored Oct 17, 2015 and Tom Rini committed Oct 19, 2015

This code is no-longer used. Drop it.

Signed-off-by: Simon Glass <sjg@chromium.org>

Paul Gortmaker authored Oct 17, 2015 and Tom Rini committed Oct 19, 2015

Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>

Paul Gortmaker authored Oct 17, 2015 and Tom Rini committed Oct 19, 2015

Between v2015.07-rc1 and v2015.07-rc2 this board started
silent boot failure.  A bisect led to commit 6eed3786
("net: Move the CMD_NET config to defconfigs").  This commit
looks harmless in itself, but it did implicitly add a feature
to the image which led to this:

 u-boot$git describe 6eed3786
 v2015.07-rc1-412-g6eed3786


              ^^^

 u-boot$ls -l ../41*/u-boot.bin
 -rwxrwxr-x 1 paul paul 261476 Oct 16 16:47 ../411/u-boot.bin
 -rwxrwxr-x 1 paul paul 266392 Oct 16 16:43 ../412/u-boot.bin
 u-boot$bc
 bc 1.06.95
 Copyright 1991-1994, 1997, 1998, 2000, 2004, 2006 Free Software Foundation, Inc.
 This is free software with ABSOLUTELY NO WARRANTY.
 For details type `warranty'.
 256*1024
 262144

i.e. we finally broke through the 256k monitor size.  Jump it
up to 384k and fix the hard coded value used in the env offset
at the same time.

We were probably flirting with the 256k size issue without
knowing it when testing on different baselines in earlier
commits, but since this is all board specific, a rebase or
reorder to put this commit 1st is of little value.

Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>

Paul Gortmaker authored Oct 17, 2015 and Tom Rini committed Oct 19, 2015

...so that I don't have to go work them out from scratch again
by peering at the manual.

Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>

Paul Gortmaker authored Oct 17, 2015 and Tom Rini committed Oct 19, 2015

When debugging an env fail due to too small a malloc pool, it
was noted that the env write was 256k.  But the device sector
size is 1/2 that, as can be seen from "fli" output:

Bank # 1: CFI conformant flash (16 x 16)  Size: 16 MB in 131 Sectors
  Intel Extended command set, Manufacturer ID: 0x89, Device ID: 0x1888
  Erase timeout: 4096 ms, write timeout: 1 ms
  Buffer write timeout: 2 ms, buffer size: 64 bytes

  Sector Start Addresses:
  FF000000 E RO   FF020000 E RO   FF040000 E RO   FF060000 E RO   FF080000 E RO
  FF0A0000 E RO   FF0C0000 E RO   FF0E0000 E RO   FF100000 E RO   FF120000 E RO
  [...]
  FFF00000   RO   FFF20000   RO   FFF40000   RO   FFF60000   RO   FFF80000   RO
  FFFA0000   RO   FFFC0000   RO   FFFE0000 E RO   FFFE8000   RO   FFFF0000 E RO
  FFFF8000   RO
=>

The desired env sector is FFF40000->FFF60000, or 0x20000 in length,
just after the 256k u-boot image which starts @ FFF00000.

Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>

Paul Gortmaker authored Oct 17, 2015 and Tom Rini committed Oct 19, 2015

Currently the board fails to save its env, since the env size
is much smaller than the sector size, and the malloc fails for
the pad buffer, giving the user visible symptom of:

Unable to save the rest of sector (253952)

Allow for 1M malloc pool, the same as used on the sbc8548 board.

Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>

Paul Gortmaker authored Oct 17, 2015 and Tom Rini committed Oct 19, 2015

It is just too painful to use interactively without it.

Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>

Andrej Rosano authored Oct 14, 2015 and Tom Rini committed Oct 19, 2015

On signature verification failures fit_image_verify() should
exit with error.

Signed-off-by: Andrej Rosano <andrej@inversepath.com>

Ladislav Michl authored Oct 12, 2015 and Tom Rini committed Oct 19, 2015

Used NAND chips requires at least 4-bit error correction, so use BCH8
as it is what kernel uses.

Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
Acked-by: Javier Martinez Canillas <javier@osg.samsung.com>

Liviu Dudau authored Oct 19, 2015 and Tom Rini committed Oct 19, 2015

Juno R1 has an XpressRICH3 PCIe host bridge that needs to be initialised
in order for the Linux kernel to be able to enumerate the bus. Add
support code here that enables the host bridge, trains the links and
sets up the Address Translation Tables.

Signed-off-by: Liviu Dudau <Liviu.Dudau@foss.arm.com>
Tested-by: Ryan Harkin <ryan.harkin@linaro.org>
[trini: Always declare vexpress64_pcie_init and continue handling logic
inside the function]
Signed-off-by: Tom Rini <trini@konsulko.com>

Liviu Dudau authored Oct 19, 2015 and Tom Rini committed Oct 19, 2015

Juno comes with 8GB RAM, but U-Boot only passes 2GB to the kernel.
Declare a secondary memory bank and set the sizes correctly.

Signed-off-by: Liviu Dudau <Liviu.Dudau@foss.arm.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Reviewed-by: Ryan Harkin <ryan.harkin@linaro.org>
Tested-by: Ryan Harkin <ryan.harkin@linaro.org>

Fabio Estevam authored Sep 23, 2015 and Tom Rini committed Oct 19, 2015

The dfu_alt_info_spl variable allows passing a starting point
for the binary to be flashed in the SPI NOR.

For example, if we have 'dfu_alt_info_spl=spl raw 0x400', this means
that we want to flash the binary starting at address 0x400.

In order to do so we need to erase the entire sector and write to
the the subsequent SPI NOR sectors taking such start address
into account for the address calculations.

Tested by succesfully writing SPL binary into 0x400 offset and
the u-boot.img at offset 64 kiB of a SPL NOR.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Lukasz Majewski <l.majewski@samsung.com>
[trini: Use lldiv for the math]
Signed-off-by: Tom Rini <trini@konsulko.com>

Fabio Estevam authored Sep 22, 2015 and Tom Rini committed Oct 19, 2015

SPI NOR flashes need to erase the entire sector size and we cannot pass
any arbitrary length for the erase operation.

To illustrate the problem:

Copying data from PC to DFU device
Download    [=========================] 100%       478208 bytes
Download done.
state(7) = dfuMANIFEST, status(0) = No error condition is present
state(10) = dfuERROR, status(14) = Something went wrong, but the
device does not know what it was
Done!

In this case, the binary has 478208 bytes and the M25P32 SPI NOR
has an erase sector of 64kB.

478208  = 7 entire sectors of 64kiB + 19456 bytes.

Erasing the first seven 64 kB sectors works fine, but when trying
to erase the remainding 19456 causes problem and the board hangs.

Fix the issue by always erasing with the erase sector size.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Lukasz Majewski <l.majewski@samsung.com>

- Add deletions from August 30 2015.
- A few from Sept 12, one from Oct 2nd.

Signed-off-by: Tom Rini <trini@konsulko.com>

Upon further review when populating README.scrapyard, inetspace_v2_cmc
is a variant on netspace_v2 and not just an orphan config.

This reverts commit 653600a7

.

Signed-off-by: Tom Rini <trini@konsulko.com>

Upon further review when populating README.scrapyard, d2net_v2 is a
variant on net2big_v2 and not just an orphan config.  To help in the
future also add this to board/LaCie/net2big_v2/MAINTAINERS which needed
a little consolidation anyhow.

This reverts commit 1363740e

.

Cc: Simon Guinot <simon.guinot@sequanux.org>
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@konsulko.com>

Add in the commit IDs / dates for boards removed on Sept 2nd.

Signed-off-by: Tom Rini <trini@konsulko.com>

Seen this one in the wild. Is labelled "Raspberry Pi Model A+ V1.1,
(C) Raspberry Pi 2014". A standard A+ board, much like the one with
version 0x12, didn't notice any differencies.

Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>

The default dockstar configuration for U-Boot currently causes it to
overrun the environment area, so that a "saveenv" command bricks the
device.  This patch moves the environment to a higher address to avoid
that.

Signed-off-by: Eric Cooper <ecc@cmu.edu>

Lokesh Vutla authored Oct 08, 2015 and Tom Rini committed Oct 17, 2015

On keystone2 Lamarr and Edison platforms, the PA clocksource
mux in PLL REG1, can be changed only after enabling its clock
domain.
So selecting the output of PASS PLL as input to PA only after
enabling the clockdomain.
This is as per the debug done by "Vitaly Andrianov <vitalya@ti.com>"
and based on the previous work done by "Hao Zhang <hzhang@ti.com>"

Fixes: d634a0775bcf ("ARM: keystone2: Cleanup PLL init code")
Reported-by: Vitaly Andrianov <vitalya@ti.com>
Tested-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>

There are various toolchain issues that cause us to produce invalid
binaries with certain gcc 4.8.x and 4.9.x versions when we don't pass
this flag in.

Tested-by: Joakim Tjernlund <joakim.tjernlund@transmode.se>
Signed-off-by: Tom Rini <trini@konsulko.com>

We need "u-boot,dm-pre-reloc" in the socfpga_cyclone5_socdk.dts file in
order for the SPL to use SD/MMC.

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>

Update the L2 AUX CTRL settings for the SoCFPGA.

Enabling D and I prefetch bits helps improve SDRAM performance on the
platform.

Also, we need to enable bit 22 of the L2. By not having bit 22 set in the
PL310 Auxiliary Control register (shared attribute override enable) has the
side effect of transforming Normal Shared Non-cacheable reads into Cacheable
no-allocate reads.

Coherent DMA buffers in Linux always have a Cacheable alias via the
kernel linear mapping and the processor can speculatively load cache
lines into the PL310 controller. With bit 22 cleared, Non-cacheable
reads would unexpectedly hit such cache lines leading to buffer
corruption.

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>

Anthony Felice authored Oct 09, 2015 and Tom Rini committed Oct 16, 2015

This commit fixes a typo in vf610twr DRAM init that was causing a hang in
U-Boot for the Vybrid Tower. This typo was introduced in commit 3f353cec


(vf610: refactor DDRMC code).

Signed-off-by: Anthony Felice <tony.felice@timesys.com>
Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>