• Screwtape's avatar
    Update to v103r03 release. · 78f34148
    Screwtape authored
    byuu says:
      - md/psg: fixed output frequency rate regression from v103r02
      - processor/m68k: fixed calculations for ABCD, NBCD, SBCD [hex\_usr,
      - processor/spc700: renamed abbreviated instructions to functional
        descriptions (eg `XCN` → `ExchangeNibble`)
      - processor/spc700: removed memory.cpp shorthand functions (fetch,
        load, store, pull, push)
      - processor/spc700: updated all instructions to follow cycle behavior
        as documented by Overload with a logic analyzer
    Once again, the changes to the SPC700 core are really quite massive. And
    this time it's not just cosmetic: the idle cycles have been updated to
    pull from various memory addresses. This is why I removed the shorthand
    functions -- so that I could handle the at-times very bizarre addresses
    the SPC700 has on its address bus during its idle cycles.
    There is one behavior Overload mentioned that I don't emulate ... one of
    the cycles of the (X) transfer functions seems to not actually access
    the $f0-ff internal SMP registers? I don't fully understand what
    Overload is getting at, so I haven't tried to support it just yet.
    Also, there are limits to logic analyzers. In many cases the same
    address is read from twice consecutively. It is unclear which of the two
    reads the SPC700 actually utilizes. I tried to choose the most logical
    values (usually the first one), but ... I don't know that we'll be able
    to figure this one out. It's going to be virtually impossible to test
    this through software, because the PC can't really execute out of
    registers that have side effects on reads.
serialization.cpp 331 Bytes