Commit 6871e0e3 authored by Tim Allen's avatar Tim Allen

Update to v106r78 release.

byuu says:

I've implemented a lot more TLCS900H instructions. There are currently
20 missing spots, all of which are unique instructions (well, MINC and
MDEC could be considered pairs of 3 each), from a map of 1024 slots.

After that, I have to write the disassembler. Then the memory bus. Then
I get to start the fun process of debugging this monstrosity.

Also new is nall/inline-if.hpp. Note that this file is technically a war
crime, so be careful when opening it. This replaces ternary() from the
previous WIP.
parent bb1dd8c6
Pipeline #43216055 passed with stage
in 11 minutes and 59 seconds
......@@ -30,7 +30,7 @@ using namespace nall;
namespace Emulator {
static const string Name = "higan";
static const string Version = "106.77";
static const string Version = "106.78";
static const string Author = "byuu";
static const string License = "GPLv3";
static const string Website = "https://byuu.org/";
......
......@@ -104,7 +104,7 @@ auto PPU::Background::affine(uint x, uint y) -> void {
}
uint screenSize = 16 << io.screenSize;
uint screenWrap = (1 << ternary(io.affineWrap, 7 + io.screenSize, 20)) - 1;
uint screenWrap = (1 << if(io.affineWrap, 7 + io.screenSize, 20)) - 1;
uint cx = (fx >> 8) & screenWrap;
uint cy = (fy >> 8) & screenWrap;
......@@ -148,7 +148,7 @@ auto PPU::Background::bitmap(uint x, uint y) -> void {
uint height = io.mode == 5 ? 128 : 160;
uint mode = depth ? Half : Byte;
uint baseAddress = ternary(io.mode == 3, 0, 0xa000 * io.frame);
uint baseAddress = if(io.mode == 3, 0, 0xa000 * io.frame);
uint px = fx >> 8;
uint py = fy >> 8;
......
......@@ -8,7 +8,7 @@ auto PPU::Objects::scanline(uint y) -> void {
if(object.affine == 0 && object.affineSize == 1) continue; //hidden
if(py >= object.height << object.affineSize) continue; //offscreen
uint rowSize = ternary(io.mapping == 0, 32 >> object.colors, object.width >> 3);
uint rowSize = if(io.mapping == 0, 32 >> object.colors, object.width >> 3);
uint baseAddress = object.character << 5;
if(object.mosaic && io.mosaicHeight) {
......
#include <gba/gba.hpp>
#include <nall/inline-if.hpp>
//pixel: 4 cycles
......
......@@ -70,7 +70,7 @@ auto VDP::Background::run(uint x, uint y) -> void {
uint16 tileData = vdp.vram.read(tileAddress);
uint4 color = tileData >> (((pixelX & 3) ^ 3) << 2);
output.color = ternary(color, tileAttributes.bits(13,14) << 4 | color, 0);
output.color = if(color, tileAttributes.bits(13,14) << 4 | color, 0);
output.priority = tileAttributes.bit(15);
}
......
#include <md/md.hpp>
#include <nall/inline-if.hpp>
namespace MegaDrive {
......
......@@ -27,7 +27,7 @@ auto YM2612::Channel::Operator::trigger(bool state) -> void {
}
auto YM2612::Channel::Operator::runEnvelope() -> void {
uint sustain = ternary(envelope.sustainLevel < 15, envelope.sustainLevel << 5, 0x3f0);
uint sustain = if(envelope.sustainLevel < 15, envelope.sustainLevel << 5, 0x3f0);
if(ym2612.envelope.clock & (1 << envelope.divider) - 1) return;
uint value = ym2612.envelope.clock >> envelope.divider;
......@@ -121,7 +121,7 @@ auto YM2612::Channel::Operator::updatePhase() -> void {
phase.delta = pitch.value + (pm >> 10 - msb) << 6 >> 7 - octave.value;
phase.delta = (!detune.bit(2) ? phase.delta + tuning : phase.delta - tuning) & 0x1ffff;
phase.delta = ternary(multiple, phase.delta * multiple, phase.delta >> 1) & 0xfffff;
phase.delta = if(multiple, phase.delta * multiple, phase.delta >> 1) & 0xfffff;
}
auto YM2612::Channel::Operator::updateLevel() -> void {
......
#include <md/md.hpp>
#include <nall/inline-if.hpp>
namespace MegaDrive {
......@@ -64,7 +65,7 @@ auto YM2612::sample() -> void {
auto wave = [&](uint n, uint modulation) -> int {
int x = (modulation >> 1) + (op[n].phase.value >> 10);
int y = sine[x & 0x3ff] + op[n].outputLevel;
return ternary(y < 0x2000, pow2[y & 0x1ff] << 2 >> (y >> 9), 0);
return if(y < 0x2000, pow2[y & 0x1ff] << 2 >> (y >> 9), 0);
};
int feedback = modMask & op[0].output + op[0].prior >> 9 - channel.feedback;
......
......@@ -13,8 +13,8 @@ auto ARM7TDMI::ADD(uint32 source, uint32 modify, bool carry) -> uint32 {
auto ARM7TDMI::ASR(uint32 source, uint8 shift) -> uint32 {
carry = cpsr().c;
if(shift == 0) return source;
carry = ternary(shift > 32, source & 1 << 31, source & 1 << shift - 1);
source = ternary(shift > 31, (int32)source >> 31, (int32)source >> shift);
carry = if(shift > 32, source & 1 << 31, source & 1 << shift - 1);
source = if(shift > 31, (int32)source >> 31, (int32)source >> shift);
return source;
}
......@@ -30,16 +30,16 @@ auto ARM7TDMI::BIT(uint32 result) -> uint32 {
auto ARM7TDMI::LSL(uint32 source, uint8 shift) -> uint32 {
carry = cpsr().c;
if(shift == 0) return source;
carry = ternary(shift > 32, 0, source & 1 << 32 - shift);
source = ternary(shift > 31, 0, source << shift);
carry = if(shift > 32, 0, source & 1 << 32 - shift);
source = if(shift > 31, 0, source << shift);
return source;
}
auto ARM7TDMI::LSR(uint32 source, uint8 shift) -> uint32 {
carry = cpsr().c;
if(shift == 0) return source;
carry = ternary(shift > 32, 0, source & 1 << shift - 1);
source = ternary(shift > 31, 0, source >> shift);
carry = if(shift > 32, 0, source & 1 << shift - 1);
source = if(shift > 31, 0, source >> shift);
return source;
}
......
#include <processor/processor.hpp>
#include <nall/inline-if.hpp>
#include "arm7tdmi.hpp"
namespace Processor {
......
......@@ -570,7 +570,7 @@ auto SPC700::instructionTestSetBitsAbsolute(bool set) -> void {
ZF = (A - data) == 0;
NF = (A - data) & 0x80;
read(address);
write(address, ternary(set, data | A, data & ~A));
write(address, if(set, data | A, data & ~A));
}
auto SPC700::instructionTransfer(uint8& from, uint8& to) -> void {
......
#include <processor/processor.hpp>
#include <nall/inline-if.hpp>
#include "spc700.hpp"
namespace Processor {
......
......@@ -23,13 +23,13 @@ template<typename T> auto TLCS900H::algorithmAdd(T target, T source, uint1 carry
T result = target + source + carry;
T carries = target ^ source ^ result;
T overflow = (target ^ result) & (source ^ result);
CF = T(carries ^ overflow).negative();
CF = T(carries ^ overflow).bit(-1);
NF = 0;
VF = overflow.negative();
VF = overflow.bit(-1);
HF = carries.bit(4);
if constexpr(T::bits() == 32) HF = Undefined;
ZF = result.zero();
SF = result.negative();
ZF = result == 0;
SF = result.bit(-1);
return result;
}
......@@ -39,8 +39,8 @@ template<typename T> auto TLCS900H::algorithmAnd(T target, T source) -> T {
NF = 0;
PF = parity(result);
HF = 1;
ZF = result.zero();
SF = result.negative();
ZF = result == 0;
SF = result.bit(-1);
return result;
}
......@@ -48,10 +48,10 @@ template<typename T> auto TLCS900H::algorithmDecrement(T target, T source) -> T
T result = target - source;
if constexpr(T::bits() == 8) {
NF = 1;
VF = T((target ^ source) & (target ^ result)).negative();
VF = T((target ^ source) & (target ^ result)).bit(-1);
HF = T(target ^ source ^ result).bit(4);
ZF = result.zero();
SF = result.negative();
ZF = result == 0;
SF = result.bit(-1);
}
return result;
}
......@@ -60,10 +60,10 @@ template<typename T> auto TLCS900H::algorithmIncrement(T target, T source) -> T
T result = target + source;
if constexpr(T::bits() == 8) {
NF = 0;
VF = T((target ^ result) & (source ^ result)).negative();
VF = T((target ^ result) & (source ^ result)).bit(-1);
HF = T(target ^ source ^ result).bit(4);
ZF = result.zero();
SF = result.negative();
ZF = result == 0;
SF = result.bit(-1);
}
return result;
}
......@@ -74,8 +74,26 @@ template<typename T> auto TLCS900H::algorithmOr(T target, T source) -> T {
NF = 0;
PF = parity(result);
HF = 0;
ZF = result.zero();
SF = result.negative();
ZF = result == 0;
SF = result.bit(-1);
return result;
}
template<typename T> auto TLCS900H::algorithmRotated(T result) -> T {
NF = 0;
PF = parity(result);
HF = 0;
ZF = result == 0;
SF = result.bit(-1);
return result;
}
template<typename T> auto TLCS900H::algorithmShifted(T result) -> T {
NF = 0;
PF = parity(result);
HF = 0;
ZF = result == 0;
SF = result.bit(-1);
return result;
}
......@@ -83,13 +101,13 @@ template<typename T> auto TLCS900H::algorithmSubtract(T target, T source, uint1
T result = target - source - carry;
T carries = target ^ source ^ result;
T overflow = (target ^ result) & (source ^ target);
CF = T(carries ^ overflow).negative();
CF = T(carries ^ overflow).bit(-1);
NF = 1;
VF = overflow.negative();
VF = overflow.bit(-1);
HF = carries.bit(4);
if constexpr(T::bits() == 32) HF = Undefined;
ZF = result.zero();
SF = result.negative();
ZF = result == 0;
SF = result.bit(-1);
return result;
}
......@@ -99,7 +117,7 @@ template<typename T> auto TLCS900H::algorithmXor(T target, T source) -> T {
NF = 0;
PF = parity(result);
HF = 0;
ZF = result.zero();
SF = result.negative();
ZF = result == 0;
SF = result.bit(-1);
return result;
}
......@@ -323,12 +323,63 @@ auto TLCS900H::instructionRegister(R register) -> void {
case 0x1a: case 0x1b: return (void)Undefined;
//case 0x1c: DJNZ r,d
case 0x1d: case 0x1e: case 0x1f: return (void)Undefined;
case 0x20:
if constexpr(bits != 32) return instructionAndCarry(register, fetchImmediate<uint8>());
return (void)Undefined;
case 0x21:
if constexpr(bits != 32) return instructionOrCarry(register, fetchImmediate<uint8>());
return (void)Undefined;
case 0x22:
if constexpr(bits != 32) return instructionXorCarry(register, fetchImmediate<uint8>());
return (void)Undefined;
case 0x23:
if constexpr(bits != 32) return instructionLoadCarry(register, fetchImmediate<uint8>());
return (void)Undefined;
case 0x24:
if constexpr(bits != 32) return instructionStoreCarry(register, fetchImmediate<uint8>());
return (void)Undefined;
case 0x25: case 0x26: case 0x27: return (void)Undefined;
case 0x28:
if constexpr(bits != 32) return instructionAndCarry(register, A);
return (void)Undefined;
case 0x29:
if constexpr(bits != 32) return instructionOrCarry(register, A);
return (void)Undefined;
case 0x2a:
if constexpr(bits != 32) return instructionXorCarry(register, A);
return (void)Undefined;
case 0x2b:
if constexpr(bits != 32) return instructionLoadCarry(register, A);
return (void)Undefined;
case 0x2c:
if constexpr(bits != 32) return instructionStoreCarry(register, A);
return (void)Undefined;
case 0x2d: return (void)Undefined;
case 0x2e: return instructionLoad(toControlRegister<T>(data), register);
case 0x2f: return instructionLoad(register, toControlRegister<T>(data));
case 0x30:
if constexpr(bits != 32) return instructionReset(register, fetchImmediate<uint8>());
return (void)Undefined;
case 0x31:
if constexpr(bits != 32) return instructionSet(register, fetchImmediate<uint8>());
return (void)Undefined;
case 0x32:
if constexpr(bits != 32) return instructionChange(register, fetchImmediate<uint8>());
return (void)Undefined;
case 0x33:
if constexpr(bits != 32) return instructionBit(register, fetchImmediate<uint8>());
return (void)Undefined;
case 0x34:
if constexpr(bits != 32) return instructionTestSet(register, fetchImmediate<uint8>());
return (void)Undefined;
case 0x35: case 0x36: case 0x37: return (void)Undefined;
//case 0x38: MINC1 #,r
//case 0x39: MINC2 #,r
//case 0x3a: MINC4 #,r
case 0x3b: return (void)Undefined;
//case 0x3c: MDEC1 #,r
//case 0x3d: MDEC2 #,r
//case 0x3e: MDEC4 #,r
case 0x3f: return (void)Undefined;
case 0x40: case 0x41: case 0x42: case 0x43: case 0x44: case 0x45: case 0x46: case 0x47:
if constexpr(bits != 32) return instructionMultiply(toRegister3<T>(data), register);
......@@ -363,7 +414,7 @@ auto TLCS900H::instructionRegister(R register) -> void {
case 0xa8: case 0xa9: case 0xaa: case 0xab: case 0xac: case 0xad: case 0xae: case 0xaf:
return instructionLoad(register, toImmediate<T>((uint3)data));
case 0xb0: case 0xb1: case 0xb2: case 0xb3: case 0xb4: case 0xb5: case 0xb6: case 0xb7:
return instructionSubtractCarry(toRegister3<T>(data), register);
return instructionSubtractBorrow(toRegister3<T>(data), register);
case 0xb8: case 0xb9: case 0xba: case 0xbb: case 0xbc: case 0xbd: case 0xbe: case 0xbf:
if constexpr(bits == 32) return (void)Undefined;
return instructionExchange(toRegister3<T>(data), register);
......@@ -372,7 +423,7 @@ auto TLCS900H::instructionRegister(R register) -> void {
case 0xc8: return instructionAdd(register, fetchImmediate<T>());
case 0xc9: return instructionAddCarry(register, fetchImmediate<T>());
case 0xca: return instructionSubtract(register, fetchImmediate<T>());
case 0xcb: return instructionSubtractCarry(register, fetchImmediate<T>());
case 0xcb: return instructionSubtractBorrow(register, fetchImmediate<T>());
case 0xcc: return instructionAnd(register, fetchImmediate<T>());
case 0xcd: return instructionXor(register, fetchImmediate<T>());
case 0xce: return instructionOr(register, fetchImmediate<T>());
......@@ -383,8 +434,24 @@ auto TLCS900H::instructionRegister(R register) -> void {
return instructionCompare(register, toImmediate<T>((uint3)data));
case 0xe0: case 0xe1: case 0xe2: case 0xe3: case 0xe4: case 0xe5: case 0xe6: case 0xe7:
return instructionOr(toRegister3<T>(data), register);
case 0xe8: return instructionRotateLeftWithoutCarry(register, fetchImmediate<uint8>());
case 0xe9: return instructionRotateRightWithoutCarry(register, fetchImmediate<uint8>());
case 0xea: return instructionRotateLeft(register, fetchImmediate<uint8>());
case 0xeb: return instructionRotateRight(register, fetchImmediate<uint8>());
case 0xec: return instructionShiftLeftArithmetic(register, fetchImmediate<uint8>());
case 0xed: return instructionShiftRightArithmetic(register, fetchImmediate<uint8>());
case 0xee: return instructionShiftLeftLogical(register, fetchImmediate<uint8>());
case 0xef: return instructionShiftRightLogical(register, fetchImmediate<uint8>());
case 0xf0: case 0xf1: case 0xf2: case 0xf3: case 0xf4: case 0xf5: case 0xf6: case 0xf7:
return instructionCompare(toRegister3<T>(data), register);
case 0xf8: return instructionRotateLeftWithoutCarry(register, A);
case 0xf9: return instructionRotateRightWithoutCarry(register, A);
case 0xfa: return instructionRotateLeft(register, A);
case 0xfb: return instructionRotateRight(register, A);
case 0xfc: return instructionShiftLeftArithmetic(register, A);
case 0xfd: return instructionShiftRightArithmetic(register, A);
case 0xfe: return instructionShiftLeftLogical(register, A);
case 0xff: return instructionShiftRightLogical(register, A);
}
}
......@@ -400,7 +467,17 @@ auto TLCS900H::instructionSourceMemory(M memory) -> void {
if constexpr(bits == 32) return (void)Undefined;
return instructionPush(memory);
case 0x05: return (void)Undefined;
//case 0x06: RLD A,(mem)
//case 0x07: RRD A,(mem)
case 0x08: case 0x09: case 0x0a: case 0x0b: case 0x0c: case 0x0d: case 0x0e: case 0x0f: return (void)Undefined;
//case 0x10: LDI
//case 0x11: LDIR
//case 0x12: LDIR
//case 0x13: LDDR
//case 0x14: CPI
//case 0x15: CPIR
//case 0x16: CPD
//case 0x17: CPDR
case 0x18: return (void)Undefined;
case 0x19:
if constexpr(bits == 32) return (void)Undefined;
......@@ -423,7 +500,7 @@ auto TLCS900H::instructionSourceMemory(M memory) -> void {
return instructionSubtract(memory, fetchImmediate<T>());
case 0x3b:
if constexpr(bits == 32) return (void)Undefined;
return instructionSubtractCarry(memory, fetchImmediate<T>());
return instructionSubtractBorrow(memory, fetchImmediate<T>());
case 0x3c:
if constexpr(bits == 32) return (void)Undefined;
return instructionAnd(memory, fetchImmediate<T>());
......@@ -453,6 +530,30 @@ auto TLCS900H::instructionSourceMemory(M memory) -> void {
case 0x68: case 0x69: case 0x6a: case 0x6b: case 0x6c: case 0x6d: case 0x6e: case 0x6f:
return instructionDecrement(memory, toImmediate<T>((uint3)data));
case 0x70: case 0x71: case 0x72: case 0x73: case 0x74: case 0x75: case 0x76: case 0x77: return (void)Undefined;
case 0x78:
if constexpr(bits != 32) return instructionRotateLeftWithoutCarry(memory, toImmediate<uint4>(1));
return (void)Undefined;
case 0x79:
if constexpr(bits != 32) return instructionRotateRightWithoutCarry(memory, toImmediate<uint4>(1));
return (void)Undefined;
case 0x7a:
if constexpr(bits != 32) return instructionRotateLeft(memory, toImmediate<uint4>(1));
return (void)Undefined;
case 0x7b:
if constexpr(bits != 32) return instructionRotateRight(memory, toImmediate<uint4>(1));
return (void)Undefined;
case 0x7c:
if constexpr(bits != 32) return instructionShiftLeftArithmetic(memory, toImmediate<uint4>(1));
return (void)Undefined;
case 0x7d:
if constexpr(bits != 32) return instructionShiftRightArithmetic(memory, toImmediate<uint4>(1));
return (void)Undefined;
case 0x7e:
if constexpr(bits != 32) return instructionShiftLeftLogical(memory, toImmediate<uint4>(1));
return (void)Undefined;
case 0x7f:
if constexpr(bits != 32) return instructionShiftRightLogical(memory, toImmediate<uint4>(1));
return (void)Undefined;
case 0x80: case 0x81: case 0x82: case 0x83: case 0x84: case 0x85: case 0x86: case 0x87:
return instructionAdd(toRegister3<T>(data), memory);
case 0x88: case 0x89: case 0x8a: case 0x8b: case 0x8c: case 0x8d: case 0x8e: case 0x8f:
......@@ -466,9 +567,9 @@ auto TLCS900H::instructionSourceMemory(M memory) -> void {
case 0xa8: case 0xa9: case 0xaa: case 0xab: case 0xac: case 0xad: case 0xae: case 0xaf:
return instructionSubtract(memory, toRegister3<T>(data));
case 0xb0: case 0xb1: case 0xb2: case 0xb3: case 0xb4: case 0xb5: case 0xb6: case 0xb7:
return instructionSubtractCarry(toRegister3<T>(data), memory);
return instructionSubtractBorrow(toRegister3<T>(data), memory);
case 0xb8: case 0xb9: case 0xba: case 0xbb: case 0xbc: case 0xbd: case 0xbe: case 0xbf:
return instructionSubtractCarry(memory, toRegister3<T>(data));
return instructionSubtractBorrow(memory, toRegister3<T>(data));
case 0xc0: case 0xc1: case 0xc2: case 0xc3: case 0xc4: case 0xc5: case 0xc6: case 0xc7:
return instructionAnd(toRegister3<T>(data), memory);
case 0xc8: case 0xc9: case 0xca: case 0xcb: case 0xcc: case 0xcd: case 0xce: case 0xcf:
......@@ -509,6 +610,11 @@ auto TLCS900H::instructionTargetMemory(uint32 address) -> void {
case 0x18: case 0x19: case 0x1a: case 0x1b: case 0x1c: case 0x1d: case 0x1e: case 0x1f: return (void)Undefined;
case 0x20: case 0x21: case 0x22: case 0x23: case 0x24: case 0x25: case 0x26: case 0x27:
return instructionLoad(toRegister3<uint16>(data), toMemory<uint16>(address));
case 0x28: return instructionAndCarry(toMemory<uint8>(address), A);
case 0x29: return instructionOrCarry(toMemory<uint8>(address), A);
case 0x2a: return instructionXorCarry(toMemory<uint8>(address), A);
case 0x2b: return instructionLoadCarry(toMemory<uint8>(address), A);
case 0x2c: return instructionStoreCarry(toMemory<uint8>(address), A);
case 0x2d: case 0x2e: case 0x2f: return (void)Undefined;
case 0x30: case 0x31: case 0x32: case 0x33: case 0x34: case 0x35: case 0x36: case 0x37:
return instructionLoad(toRegister3<uint32>(data), toMemory<uint32>(address));
......@@ -524,6 +630,26 @@ auto TLCS900H::instructionTargetMemory(uint32 address) -> void {
case 0x68: case 0x69: case 0x6a: case 0x6b: case 0x6c: case 0x6d: case 0x6e: case 0x6f: return (void)Undefined;
case 0x70: case 0x71: case 0x72: case 0x73: case 0x74: case 0x75: case 0x76: case 0x77: return (void)Undefined;
case 0x78: case 0x79: case 0x7a: case 0x7b: case 0x7c: case 0x7d: case 0x7e: case 0x7f: return (void)Undefined;
case 0x80: case 0x81: case 0x82: case 0x83: case 0x84: case 0x85: case 0x86: case 0x87:
return instructionAndCarry(toMemory<uint8>(address), toImmediate<uint3>(data));
case 0x88: case 0x89: case 0x8a: case 0x8b: case 0x8c: case 0x8d: case 0x8e: case 0x8f:
return instructionOrCarry(toMemory<uint8>(address), toImmediate<uint3>(data));
case 0x90: case 0x91: case 0x92: case 0x93: case 0x94: case 0x95: case 0x96: case 0x97:
return instructionXorCarry(toMemory<uint8>(address), toImmediate<uint3>(data));
case 0x98: case 0x99: case 0x9a: case 0x9b: case 0x9c: case 0x9d: case 0x9e: case 0x9f:
return instructionLoadCarry(toMemory<uint8>(address), toImmediate<uint3>(data));
case 0xa0: case 0xa1: case 0xa2: case 0xa3: case 0xa4: case 0xa5: case 0xa6: case 0xa7:
return instructionStoreCarry(toMemory<uint8>(address), toImmediate<uint3>(data));
case 0xa8: case 0xa9: case 0xaa: case 0xab: case 0xac: case 0xad: case 0xae: case 0xaf:
return instructionTestSet(toMemory<uint8>(address), toImmediate<uint3>(data));
case 0xb0: case 0xb1: case 0xb2: case 0xb3: case 0xb4: case 0xb5: case 0xb6: case 0xb7:
return instructionReset(toMemory<uint8>(address), toImmediate<uint3>(data));
case 0xb8: case 0xb9: case 0xba: case 0xbb: case 0xbc: case 0xbd: case 0xbe: case 0xbf:
return instructionSet(toMemory<uint8>(address), toImmediate<uint3>(data));
case 0xc0: case 0xc1: case 0xc2: case 0xc3: case 0xc4: case 0xc5: case 0xc6: case 0xc7:
return instructionChange(toMemory<uint8>(address), toImmediate<uint3>(data));
case 0xc8: case 0xc9: case 0xca: case 0xcb: case 0xcc: case 0xcd: case 0xce: case 0xcf:
return instructionBit(toMemory<uint8>(address), toImmediate<uint3>(data));
case 0xd0: case 0xd1: case 0xd2: case 0xd3: case 0xd4: case 0xd5: case 0xd6: case 0xd7:
case 0xd8: case 0xd9: case 0xda: case 0xdb: case 0xdc: case 0xdd: case 0xde: case 0xdf:
return instructionJump((uint4)data, toMemory<uint32>(address));
......
......@@ -13,6 +13,21 @@ auto TLCS900H::instructionAnd(Target target, Source source) -> void {
store(target, algorithmAnd(load(target), load(source)));
}
template<typename Source, typename Offset>
auto TLCS900H::instructionAndCarry(Source source, Offset offset) -> void {
if constexpr(Source::bits == 8 && is_same_v<Offset, Register<uint8>>) { if(load(offset).bit(3)) return (void)Undefined; }
CF &= load(source).bit(load(offset) & Source::bits - 1);
}
template<typename Source, typename Offset>
auto TLCS900H::instructionBit(Source source, Offset offset) -> void {
NF = 0;
VF = Undefined;
HF = 1;
ZF = !load(source).bit(load(offset) & Source::bits - 1);
SF = Undefined;
}
auto TLCS900H::instructionBitSearch1Backward(Register<uint16> register) -> void {
auto value = load(register);
for(uint index : reverse(range(16))) {
......@@ -41,6 +56,13 @@ auto TLCS900H::instructionCallRelative(Source displacement) -> void {
store(PC, load(PC) + load(displacement));
}
template<typename Target, typename Offset>
auto TLCS900H::instructionChange(Target target, Offset offset) -> void {
auto result = load(target);
result.bit(load(offset) & Target::bits - 1) ^= 1;
store(target, result);
}
template<typename Target, typename Source>
auto TLCS900H::instructionCompare(Target target, Source source) -> void {
algorithmSubtract(load(target), load(source));
......@@ -59,8 +81,8 @@ auto TLCS900H::instructionDecimalAdjustAccumulator(Register<uint8> register) ->
if(HF || (uint4)value > 0x09) value += NF ? -0x06 : 0x06;
PF = parity(value);
HF = uint8(value ^ load(register)).bit(4);
ZF = value.zero();
SF = value.negative();
ZF = value == 0;
SF = value.bit(-1);
store(register, value);
}
......@@ -139,6 +161,12 @@ auto TLCS900H::instructionLoad(Target target, Source source) -> void {
store(target, load(source));
}
template<typename Source, typename Offset>
auto TLCS900H::instructionLoadCarry(Source source, Offset offset) -> void {
if constexpr(Source::bits == 8 && is_same_v<Offset, Register<uint8>>) { if(load(offset).bit(3)) return (void)Undefined; }
CF = load(source).bit(load(offset) & Source::bits - 1);
}
//reverse all bits in a 16-bit register
//note: an 8-bit lookup table is faster (when in L1/L2 cache), but much more code
auto TLCS900H::instructionMirror(Register<uint16> register) -> void {
......@@ -163,9 +191,9 @@ auto TLCS900H::instructionMultiplyAdd(Register<uint16> register) -> void {
store(XHL, load(XHL) - 2);
auto result = load(expand(register));
VF = uint32(~(target ^ source) & (target ^ result)).negative();
ZF = result.zero();
SF = result.negative();
VF = uint32((target ^ result) & (source ^ result)).bit(-1);
ZF = result == 0;
SF = result.bit(-1);
}
template<typename Target, typename Source>
......@@ -186,6 +214,12 @@ auto TLCS900H::instructionOr(Target target, Source source) -> void {
store(target, algorithmOr(load(target), load(source)));
}
template<typename Source, typename Offset>
auto TLCS900H::instructionOrCarry(Source source, Offset offset) -> void {
if constexpr(Source::bits == 8 && is_same_v<Offset, Register<uint8>>) { if(load(offset).bit(3)) return (void)Undefined; }
CF |= load(source).bit(load(offset) & Source::bits - 1);
}
template<typename Target>