# Background For most of A-Core development, there has been only one SoC-level target called `ACoreChip`. `ACoreChip` is a configurable SoC that contains the A-Core processor (`ACoreBase`) and a configurable set of memories and other peripherals required to use the processor. During development, the configuration between `ACoreBase` and `ACoreChip` has become intertwined. Currently, there is a single configuration structure [`ACoreConfig`](https://gitlab.com/a-core/a-core_chisel/a_core_common/-/blob/4431b08543bdcdefc05f46fcb6b1d6a0ae41181f/src/main/scala/a_core_common/a_core_config.scala) that contains both core-level configuration (e.g. used ISA extensions, initial value of program counter, ...) and chip-level configuration (memory sizes, peripheral device configuration, ...). This makes it very hard to build other SoC architectures around the processor, because in order to use the core, one needs to provide configuration that assumes a given SoC architecture. There is thus need to decouple chip-level configuration from core-level configuration. `ACoreConfig` should _only_ contain processor configuration, and the chip-level configuration should be moved to `ACoreChip` repository. ## Changes - [x] Move system-level configuration from `ACoreConfig` to `ACoreChip` repo - [x] Move remaining core-level `ACoreConfig` to `ACoreBase` repo - [x] Move (data) `CacheConfig` to repo where the DCache is being developed (ACoreChip?) ## Related Issues - [x] a-core/a-core_chisel/a_core_common#2 ## Merge Requests - ~~https://gitlab.com/a-core/a-core_chisel/a_core_common/-/merge_requests/20~~ - ~~https://gitlab.com/a-core/a-core_chisel/ACoreBase/-/merge_requests/61~~ - https://gitlab.com/a-core/a-core_chisel/acoreblocks/-/merge_requests/3 - https://gitlab.com/a-core/a-core_chisel/ACoreChip/-/merge_requests/45