Commit 556f1386 authored by Daniel Engberg's avatar Daniel Engberg
Browse files

cad/yosys-systemverilog: Remove from tree 

Broken for years in tree, no PR of fixing it
parent 3666da28

MOVED

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@@ -5743,3 +5743,4 @@ textproc/py-pypa-docs-theme||2026-10-15|Has expired: Upstream archived the repo 
www/py-wikitools||2026-10-18|Has expired: Not compatible with Python 3

japanese/fcitx-mozc|japanese/fcitx5-mozc|2026-10-18|Deprecated: Use fcitx5 instead

benchmarks/mangohud||2026-10-19|Broken for years in tree

cad/yosys-systemverilog||2026-10-19|Broken for years in tree

cad/Makefile

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@@ -167,7 +167,6 @@ 
    SUBDIR += xyce

    SUBDIR += yosys

    SUBDIR += yosys-ghdl-plugin

    SUBDIR += yosys-systemverilog

    SUBDIR += z88

    SUBDIR += zcad

cad/yosys-systemverilog/Makefile

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Changes for cad/yosys-systemverilog/Makefile: 0 added lines, 98 removed lines.
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PORTNAME=	yosys-systemverilog

DISTVERSION=	2023-06-14

PORTREVISION=	2

CATEGORIES=	cad

PKGNAMEPREFIX=



MAINTAINER=	yuri@FreeBSD.org

COMMENT=	SystemVerilog support for Yosys

WWW=		https://github.com/antmicro/yosys-systemverilog



LICENSE=	APACHE20

LICENSE_FILE=	${WRKSRC}/LICENSE



BROKEN=		incompatible yet with the latest cad/uhdm, see https://github.com/antmicro/yosys-systemverilog/issues/1845



BUILD_DEPENDS=	bash:shells/bash \

		yosys>0:cad/yosys

LIB_DEPENDS=	libcapnp.so:devel/capnproto \

		libffi.so:devel/libffi \

		libsurelog.so:cad/surelog \

		libuhdm.so:cad/uhdm

RUN_DEPENDS=	yosys>0:cad/yosys



USES=		cabal gmake pkgconfig python:build readline tcl



USE_CABAL=	alex-3.3.0.0 \

		cmdargs-0.10.22 \

		githash-0.1.6.3 \

		happy-1.20.1.1 \

		hashable-1.4.2.0_1 \

		primitive-0.8.0.0 \

		th-compat-0.1.4_2 \

		vector-0.13.0.0_3 \

		vector-stream-0.1.0.0_2

SKIP_CABAL_PLIST=	yes

# in order to update USE_CABAL run 'make local-cabal-configure local-make-use-cabal'



USE_GITHUB=	yes

GH_ACCOUNT=	antmicro

GH_TAGNAME=	49069fb-${DISTVERSION}

GH_TUPLE=	chipsalliance:yosys-f4pga-plugins:56f957c:yosys_f4pga_plugins/yosys-f4pga-plugins \

		zachjs:sv2v:6c4ee8f:sv2v/sv2v \

		YosysHQ:yosys:c5e4eec:yosys/yosys



MAKE_ENV=	DESTDIR=${DESTDIR} \

		HOME=${WRKSRC}

MAKE_ARGS=	YOSYS_PATH=${LOCALBASE} -j${MAKE_JOBS_NUMBER}



BINARY_ALIAS=	python3=${PYTHON_CMD} \

		install=${FILESDIR}/install.sh



OPTIONS_DEFINE=		TCMALLOC

OPTIONS_DEFAULT=	TCMALLOC # should be the same TCMALLOC default as in cad/yosys, cad/surelog, cad/uhdm because surelog's lib is used in the yosys plugin cad/yosys-systemverilog



TCMALLOC_LDFLAGS=	`pkg-config --libs libtcmalloc`

TCMALLOC_LIB_DEPENDS=	libtcmalloc.so:devel/google-perftools



PORTSCOUT=	ignore:1 # until https://github.com/antmicro/yosys-systemverilog/issues/1798 is resolved



post-extract:

	@${CP} ${WRKSRC_yosys}/passes/pmgen/pmgen.py ${WRKSRC}/yosys-f4pga-plugins



local-cabal-configure: check-cabal

	@cd ${WRKSRC}/sv2v && \

		${SETENV} ${MAKE_ENV} ${CABAL_HOME_ENV} ${CABAL_CMD} build --dry-run --disable-benchmarks --disable-tests --flags="${CABAL_FLAGS}" ${CABAL_WITH_ARGS} ${CABAL_LTO_ARGS} ${BUILD_ARGS} exe:sv2v



local-make-use-cabal: check-cabal2tuple

	@${_CABAL2TUPLE_CMD} ${CABAL2TUPLE_ARGS} ${WRKSRC}/sv2v || (${ECHO_CMD} "Did you forget to make do-cabal-configure ?" ; exit 1)



do-build:

	# UHDM plugin

	${ECHO} "==> Building the C part (yosys-f4pga-plugins)"

	@cd ${WRKSRC}/yosys-f4pga-plugins && ${SETENV} ${MAKE_ENV} ${GMAKE} ${MAKE_ARGS} ${ALL_TARGET}

	# sv2v

	${ECHO} "==> Building the Haskell part (sv2v)"

	cd ${WRKSRC}/sv2v && \

		${LN} -fs ${CABAL_DEPSDIR} && \

		${LN} -fs ../cabal.project.local && \

		${SETENV} ${MAKE_ENV} ${CABAL_HOME_ENV} ${CABAL_CMD} build --offline --disable-benchmarks --disable-tests ${CABAL_WITH_ARGS} ${CABAL_LTO_ARGS} --flags "${CABAL_FLAGS}" ${BUILD_ARGS} exe:sv2v



do-install:

	# create directories

	@${MKDIR} \

		${STAGEDIR}${PREFIX}/share/yosys/plugins/fasm_extra_modules \

		${STAGEDIR}${PREFIX}/share/yosys/quicklogic/pp3 \

		${STAGEDIR}${PREFIX}/share/yosys/quicklogic/qlf_k6n10 \

		${STAGEDIR}${PREFIX}/share/yosys/quicklogic/qlf_k6n10f \

		${STAGEDIR}${PREFIX}/share/yosys/nexus

	# UHDM plugin

	cd ${WRKSRC}/yosys-f4pga-plugins && ${SETENV} ${MAKE_ENV} ${GMAKE} ${MAKE_ARGS} ${INSTALL_TARGET}

	# sv2v

	${INSTALL_PROGRAM} \

		${WRKSRC}/sv2v/dist-newstyle/build/*-freebsd/ghc-*/sv2v-*/x/sv2v/build/sv2v/sv2v \

		${STAGEDIR}${PREFIX}/bin

	# strip binaries

	${STRIP_CMD} ${STAGEDIR}${PREFIX}/share/yosys/plugins/*.so



.include <bsd.port.mk>

cad/yosys-systemverilog/distinfo

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Changes for cad/yosys-systemverilog/distinfo: 0 added lines, 35 removed lines.
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TIMESTAMP = 1687103884

SHA256 (cabal/alex-3.3.0.0/alex-3.3.0.0.tar.gz) = 810f8e85ea6b87c37cba10f7660d7f1aa0ba251c1275e3a18c312964bb329a63

SIZE (cabal/alex-3.3.0.0/alex-3.3.0.0.tar.gz) = 86004

SHA256 (cabal/cmdargs-0.10.22/cmdargs-0.10.22.tar.gz) = b8b12e7f8795cf13037bb062d453b86c788eae62558586f59e9419aabe6e9bef

SIZE (cabal/cmdargs-0.10.22/cmdargs-0.10.22.tar.gz) = 65154

SHA256 (cabal/githash-0.1.6.3/githash-0.1.6.3.tar.gz) = fcba79b60ef87bdd4976332e998589a62e1be012b932b543b49de5e0620eef1b

SIZE (cabal/githash-0.1.6.3/githash-0.1.6.3.tar.gz) = 7617

SHA256 (cabal/happy-1.20.1.1/happy-1.20.1.1.tar.gz) = 8b4e7dc5a6c5fd666f8f7163232931ab28746d0d17da8fa1cbd68be9e878881b

SIZE (cabal/happy-1.20.1.1/happy-1.20.1.1.tar.gz) = 183409

SHA256 (cabal/hashable-1.4.2.0/hashable-1.4.2.0.tar.gz) = 1b4000ea82b81f69d46d0af4152c10c6303873510738e24cfc4767760d30e3f8

SIZE (cabal/hashable-1.4.2.0/hashable-1.4.2.0.tar.gz) = 25094

SHA256 (cabal/hashable-1.4.2.0/revision/1.cabal) = 585792335d5541dba78fa8dfcb291a89cd5812a281825ff7a44afa296ab5d58a

SIZE (cabal/hashable-1.4.2.0/revision/1.cabal) = 4520

SHA256 (cabal/primitive-0.8.0.0/primitive-0.8.0.0.tar.gz) = 5553c21b4a789f9b591eed69e598cc58484c274af29250e517b5a8bcc62b995f

SIZE (cabal/primitive-0.8.0.0/primitive-0.8.0.0.tar.gz) = 57222

SHA256 (cabal/th-compat-0.1.4/th-compat-0.1.4.tar.gz) = d8f97ac14ab47b6b8a7b0fdb4ff95426322ec56badd01652ac15da4a44d4bab8

SIZE (cabal/th-compat-0.1.4/th-compat-0.1.4.tar.gz) = 14838

SHA256 (cabal/th-compat-0.1.4/revision/2.cabal) = e5ae7c083ef3a22248558f8451669bb1c55ea8090f5908b86b9033743c161730

SIZE (cabal/th-compat-0.1.4/revision/2.cabal) = 3224

SHA256 (cabal/vector-0.13.0.0/vector-0.13.0.0.tar.gz) = c5d3167d15e12f52e00879ddf304a591672a74e369cc47bc5c7fa1d5a8d15b4f

SIZE (cabal/vector-0.13.0.0/vector-0.13.0.0.tar.gz) = 154509

SHA256 (cabal/vector-0.13.0.0/revision/3.cabal) = fa5cac81a17a5af388716792e8b99c24b3b66770086756d0d8b23f8272a0244c

SIZE (cabal/vector-0.13.0.0/revision/3.cabal) = 9112

SHA256 (cabal/vector-stream-0.1.0.0/vector-stream-0.1.0.0.tar.gz) = a888210f6467f155090653734be5cc920406a07227e0d3adb59096716fdb806c

SIZE (cabal/vector-stream-0.1.0.0/vector-stream-0.1.0.0.tar.gz) = 12377

SHA256 (cabal/vector-stream-0.1.0.0/revision/2.cabal) = f5d6d5291cd1b5f2f063403593f1f5c8127d692c888eedeb3e1eb40497a88dca

SIZE (cabal/vector-stream-0.1.0.0/revision/2.cabal) = 1404

SHA256 (cabal/antmicro-yosys-systemverilog-2023-06-14-49069fb-2023-06-14_GH0.tar.gz) = 56c4b96f1be7acfee147033d1f726c82b83ee61ccc8dd18e95914f21e3c5e6b6

SIZE (cabal/antmicro-yosys-systemverilog-2023-06-14-49069fb-2023-06-14_GH0.tar.gz) = 157988

SHA256 (cabal/chipsalliance-yosys-f4pga-plugins-56f957c_GH0.tar.gz) = e2bf0adae00912e07524f2ecf5f6de3d395d283890652d38568175ad56d7bada

SIZE (cabal/chipsalliance-yosys-f4pga-plugins-56f957c_GH0.tar.gz) = 2690136

SHA256 (cabal/zachjs-sv2v-6c4ee8f_GH0.tar.gz) = b03955f19128d05c2a2c9d162b2b946fd23a220146abbc5b7847c83c3f937e90

SIZE (cabal/zachjs-sv2v-6c4ee8f_GH0.tar.gz) = 279380

SHA256 (cabal/YosysHQ-yosys-c5e4eec_GH0.tar.gz) = ad4b43d55d98d2cc6f4892c1af6b0770af994a51f0cf8d450029f2a404738b8a

SIZE (cabal/YosysHQ-yosys-c5e4eec_GH0.tar.gz) = 2542646

cad/yosys-systemverilog/files/install.sh

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Changes for cad/yosys-systemverilog/files/install.sh: 0 added lines, 14 removed lines.
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#!/bin/sh



##

## workaround for

## * https://github.com/chipsalliance/yosys-f4pga-plugins/issues/527

##

##



if [ "$1" != "-D" ]; then

	exit 1

fi



#/usr/bin/install -m 0644 $2 ${DESTDIR}$3

/usr/bin/install $2 $3