R
rtl

Projects with this topic

View ygrec8 project

fhwd / ygrec8

A Free HardWare Design of minimalist RISC 8-bit processor core for your System-on-Chip. See ygrec8.com

Bash VHDL SOC cpu ASIC asm rtl

0

Updated Dec 22, 2023

0 0 0 0

Updated Dec 22, 2023
View TrustNest project

FreeDev / platforms / TrustNest

A minimalist, workstation platform

RISC-V riscv riscv64 Risc-V64 RISC pqc post-quantum... post-quantum... post-quantum... FPGA open hardware openhardware open-hardware hardware Hardware Design microprocessor Microprocessors Scala Chisel rtl agile cxl cxl4 RVA23-compliant

1

Updated Feb 08, 2026

1 0 0 0

Updated Feb 08, 2026
View pyrift project

Regis Cattenoz / pyrift

Python Register InterFace Translation

HDL SystemVerilog systemrdl rtl

3

Updated Mar 18, 2025

3 1 0 8

Updated Mar 18, 2025
View FreeNest project

FreeDev / platforms / FreeNest

The FreeNest platform development.

RISC-V riscv riscv64 Risc-V64 pqc post-quantum... post-quantum... post-quantum... FPGA open hardware openhardware open-hardware open-source-... hardware Hardware Design microprocessor Microprocessors Scala Chisel agile rtl cxl cxl4 RVA23-compliant

1

Updated Feb 08, 2026

1 0 0 0

Updated Feb 08, 2026
View FreeBird project

FreeDev / processors / FreeBird

The FreeBird APU development.

RISC-V riscv riscv64 Risc-V64 pqc post-quantum... post-quantum... post-quantum... FPGA open hardware openhardware open-hardware hardware Hardware Design microprocessor Scala Chisel agile rtl cxl cxl4 RVA23-compliant Curvilinear curvilinear ...

1

Updated Feb 08, 2026

1 0 0 0

Updated Feb 08, 2026