F

FPGA

Open source Logic Analyzer based on LiteX SoC

A Formal Verification Methodology to lower the adoption barriers for Formal Verification of ASIC and FPGA designs in the Space sector

Collection of utility modules written in Verilog

Implementation of Intel8080 cpu written in verilog running spaceinvaders.

HACK CPU from course nand2tetris written in verilog with vga and ps/2 keyboard.

Z80 @10 MHz PoC for Altera Cyclone II and Cyclone IV (DE0-Nano board) FPGAs

VHDL generator for Gowin pROM IP Core

a fork of http://svn.clifford.at/libxsvf/trunk@104

Simple SDRAM test for Cyclone FPGA in VHDL

Using Yosys to synthesize a bitstream for a Lattice MachXO3 board

FPGA HLS Kernel for SECP256K1 Signature Verification used as part of Baldur: A Hybrid Blockchain Database with FPGA or GPU Acceleration

A simple COMmunication BLOCK with well know interfaces in the FPGA side

Set of simple modules to communicate via UART

Collection of simple interfaces for Digilent Pmods

Collection of some simple AXI4-Lite slaves.

Custom AXI GPIO core with up to 32 input and 32 output ports

Implementation of MIX as proposed in "The Art of Computer Programming, Vol. 1" by Donald E. Knuth. Runs on iCE40-fpga using only FOSS Hard- and Software.

LaTeX documentation of JSwitch IP

A VHDL synthesizable and behavioral FIFO design.