S
SDR
Projects with this topic
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Experimental Phased Clock Generator (XPCG) is an Arduino Due application for controlling a phased array of clock signals via the 5P49V60 clock generator IC with per-channel delay control in the sub-1ns regime.
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Information, faq, history, design, howto compile the SAQrx Software Define VLF receiver.
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A simple Software Define VLF Receiver using a sound card.
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A Software Define VLF Receiver using a sound card.
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A simple Software Define VLF Receiver using a sound card.
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Deploys three Docker containers to run rtl_tcp, rtlamr, and custom Python app to read the JSON output from rtlamr and store the meter reading and current daily use in an SQLite database.
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