Wanted: pipelined divider
- The divider could be remade with a pipelined architecture, to allow for easier development of the equalizer
- Probably a first stage for sign adjustment, followed by a number of iteration stages inside a generate loop, and ending in a final stage where the sign is re-adjusted back would do the trick
- The number of iteration stages depends on the generics with which the divider is instanced
- It will be desirable to keep the 'valid' signal inside the pipeline, which will also indicate whether we have valid data inside a particular pipeline stage
- A testbench must be made for the pipelined divider, to prove correct functionality. We can either compare it to the non-pipelined divider or create a new testbench. We will need also to prove correct functionality in the case of intermittently enabling the 'valid' input