Commit ceaa0962 authored by Mario's avatar Mario
Browse files

fixing some string escapes

parent d39ea879
Loading
Loading
Loading
Loading
+2 −2
Original line number Diff line number Diff line
@@ -3,7 +3,7 @@
Collects the config from 3 different locations:

* Local script directory (DMT_config.yaml).
* User's home directory (%LOCALAPPDATA%\DMT\DMT_config.yaml or $XDG_CONFIG_HOME/DMT/DMT_config.yaml with $XDG_CONFIG_HOME defaulting to ~/.config) and
* User's home directory (%LOCALAPPDATA%\\DMT\\DMT_config.yaml or $XDG_CONFIG_HOME/DMT/DMT_config.yaml with $XDG_CONFIG_HOME defaulting to ~/.config) and
* DMT package installation directory (DMT/config/DMT_config.yaml)

They are all read and finally taken in the order given here. This means that anything given in the local directory overwrites all others.
@@ -72,7 +72,7 @@ except FileNotFoundError:
        warnings.warn(
            (
                "The DMT user configuration file has been moved. The new paths are:\n"
                + "Windows: %LOCALAPPDATA%\DMT\DMT_config.yaml\n"
                + "Windows: %LOCALAPPDATA%\\DMT\\DMT_config.yaml\n"
                + "Linux and MacOS: $XDG_CONFIG_HOME/DMT/DMT_config.yaml\n"
                + "Defaulting to ~/.config/DMT/DMT_config.yaml"
            ),
+1 −1
Original line number Diff line number Diff line
@@ -1290,7 +1290,7 @@ class McParameterCollection(object):
                    else:
                        data_table.add_row(
                            [
                                NoEscape(f"{para:<12s}/\si{{{para:u}}}"),
                                NoEscape(f"{para:<12s}/\\si{{{para:u}}}"),
                                NoEscape(f"{para:g}"),
                            ],
                            strict=False,
+1 −1
Original line number Diff line number Diff line
@@ -307,7 +307,7 @@ class VAFileMap(object):
        path_to_target: Union[str, Path],
        filter: Optional[Callable[[str], str]] = None,
    ):
        """Writes the all Verilog-A files from this mapping into the given target path. The file structure is written as read from the "original"
        r"""Writes the all Verilog-A files from this mapping into the given target path. The file structure is written as read from the "original"

        Parameters
        ----------