merge new stuff (9cc6bbad) · Commits · DMT-development / DMT-core

DMT/core/data_frame.py

+54 −0

Original line number	Diff line number	Diff line
		@@ -801,6 +801,10 @@ class DataFrame(DataProcessor, pd.DataFrame):
		self = self.calc_cgd(port_1=ports[0], port_2=ports[1])
		elif nodes[0] == "G" and nodes[1] == "G": # CGG
		self = self.calc_cgg(port_1=ports[0], port_2=ports[1])
		elif nodes[0] == "D" and nodes[1] == "B": # CDB
		self = self.calc_cdb(port_1=ports[0], port_2=ports[1], port_3=ports[2])
		elif nodes[0] == "S" and nodes[1] == "B": # CSB
		self = self.calc_csb(port_1=ports[0], port_2=ports[1], port_3=ports[2])
		else:
		raise KeyError("The " + "".join(nodes) + " capacitance can not be calculated.")
		except IOError as err:
		@@ -1957,6 +1961,56 @@ class DataFrame(DataProcessor, pd.DataFrame):
		pd.options.mode.chained_assignment = "warn"
		return self

		def calc_cdb(self, port_1="G", port_2="D", port_3="B"):
		"""Calculates the drain-bulk capacitance CDB assuming PI equivalent circuit and common source configuration.

		Returns
		-------
		:class:`DMT.core.DataFrame`
		Dataframe that contains CDB.
		"""
		# get values

		sp_cdb = specifiers.CAPACITANCE + ["D", "B"]

		# put values in col of self
		pd.options.mode.chained_assignment = None
		if port_1 == "G" and port_2 == "D" and port_3 == "B":
		s_para_values = self.get_ss_para("Y", port_2, port_3)
		self[sp_cdb] = self.processor.calc_cap_series_thru(self["FREQ"], s_para_values, "Y")
		else:
		raise NotImplementedError(
		"DMT -> DataFrame -> calc_cgs: transistor configuration not implemented."
		)

		pd.options.mode.chained_assignment = "warn"
		return self

		def calc_csb(self, port_1="G", port_2="D", port_3="B"):
		"""Calculates the source-bulk capacitance CDB assuming PI equivalent circuit and common source configuration.

		Returns
		-------
		:class:`DMT.core.DataFrame`
		Dataframe that contains CDB.
		"""
		# get values

		sp_csb = specifiers.CAPACITANCE + ["S", "B"]

		# put values in col of self
		pd.options.mode.chained_assignment = None
		if port_1 == "G" and port_2 == "D" and port_3 == "B":
		s_para_values = self.get_ss_para("Y", port_2, port_3)
		self[sp_csb] = self.processor.calc_cap_shunt_port_2(self["FREQ"], s_para_values, "Y")
		else:
		raise NotImplementedError(
		"DMT -> DataFrame -> calc_cgs: transistor configuration not implemented."
		)

		pd.options.mode.chained_assignment = "warn"
		return self

		def calc_cbe(self, port_1="B", port_2="C"):
		"""Calculates the base-emitter junction capacitance CBE assuming PI equivalent circuit and common emitter configuration.

DMT/core/dut_lib.py

+6 −1

Original line number	Diff line number	Diff line
		@@ -1204,7 +1204,12 @@ class DutLib(object):

		# Makes it possible to iterate over DutLib objects
		def __iter__(self):
		return iter([dut for dut in self.duts if dut.name not in self.ignore_duts])
		return iter(
		sorted(
		[dut for dut in self.duts if dut.name not in self.ignore_duts],
		key=lambda dut: dut.name,
		)
		)

		def __getitem__(self, key):
		return self.duts[key]

DMT/core/mc_parameter.py

+13 −8

Original line number	Diff line number	Diff line
		@@ -69,7 +69,7 @@ except ImportError:
		pass

		SEMVER_MCPARAMETER_CURRENT = VersionInfo(major=1, minor=0)
		SEMVER_MCPARAMETER_Collection_CURRENT = VersionInfo(major=1, minor=0)
		SEMVER_MCPARAMETER_Collection_CURRENT = VersionInfo(major=1, minor=0, patch=1)


		class McParameter(object):
		@@ -640,7 +640,11 @@ class McParameterCollection(object):
		f"{__McParameterCollection__:1.1f}.0"
		) # if it is a number only MAJOR.MINOR is used

		if __McParameterCollection__ != SEMVER_MCPARAMETER_Collection_CURRENT:
		if __McParameterCollection__ == VersionInfo(major=1, minor=0):
		# trun around possible groups..
		if possible_groups is not None:
		possible_groups = dict([(key, item) for item, key in possible_groups.items()])
		elif __McParameterCollection__ != SEMVER_MCPARAMETER_Collection_CURRENT:
		raise NotImplementedError(
		"DMT->McParameterCollection: Unknown version of collection to create!"
		)
		@@ -1256,15 +1260,16 @@ class McParameterCollection(object):

		group = para.group
		try:
		group_desc = next(
		description
		for description, group_a in self.possible_groups.items()
		if group_a == group
		)
		# group_desc = next(
		# description
		# for description, group_a in self.possible_groups.items()
		# if group_a == group
		# )
		group_desc = self.possible_groups[group]
		data_table.add_row(
		(MultiColumn(2, align="l", data=group_desc),), strict=False
		)
		except StopIteration:
		except KeyError:
		pass

		if para.unit.dimensionless:

DMT/core/mc_skywater.py

+1 −3

Original line number	Diff line number	Diff line
		@@ -60,9 +60,7 @@ class McSkywater(MCard):
		**kwargs,
		):
		if possible_groups is None:
		possible_groups = {
		"Geometrie": "geo",
		}
		possible_groups = {"geo": "Geometrie"}

		super().__init__(
		nodes_list,

DMT/core/mcard.py

+17 −0

Original line number	Diff line number	Diff line
		@@ -319,6 +319,7 @@ class MCard(McParameterCollection):
		"""
		vae_module = self.get_verilogae_model()
		paras_new = []
		# missing_groups = []
		# Updated parameter properties
		for para_name, para_properties in vae_module.modelcard.items():
		para_name = para_name.lower()
		@@ -354,8 +355,24 @@ class MCard(McParameterCollection):
		unit=unit_converter[para_properties.unit],
		description=para_properties.description,
		)

		# if para.group not in self.possible_groups:
		# warnings.warn(
		# f"DMT->MCard: The parameter group {para.group} is not part of this modelcards possible groups.\nThis parameter group was given in the parameter {para.name}",
		# category=RuntimeWarning,
		# )
		# missing_groups.append(para.group)
		# self.possible_groups[para.group] = ""
		paras_new.append(para)

		# if missing_groups:
		# missing_groups_dict_str = '":,\n"'.join(missing_groups)
		# warnings.warn(
		# f'DMT->MCard: Full list of missing groups to copy into a dict:\n"{missing_groups_dict_str}":,\n'
		# category=RuntimeWarning,
		# stacklevel=
		# )

		if remove_old_parameters:
		self._paras = [] # remove the old parameters fast...