ramips: mediatek: Disable flow control for mt7530 switch due to mt7621 cpu bug

Signed-off-by: David Bentham <db260179@gmail.com>

target/linux/ramips/patches-5.10/701-net-ethernet-mediatek-mt7530-disable-flow-control.patch

+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -1715,6 +1715,17 @@ mt7530_setup(struct dsa_switch *ds)
+ 	val |= MHWTRAP_MANUAL;
+ 	mt7530_write(priv, MT7530_MHWTRAP, val);
+ 
++	/* Disable flow control for P5 and P6 ports - mt7621 cpu bug */
++	usleep_range(10, 20);
++
++	val = mt7530_read(priv, 0x1FE0);
++	val &= ~BIT(31);
++	mt7530_write(priv, 0x1FE0, val);
++
++	mt7530_write(priv, MT7530_PMCR_P(5), 0x5e30b);
++	mt7530_write(priv, MT7530_PMCR_P(6), 0x5e30b);
++	usleep_range(10, 20);
++
+ 	priv->p6_interface = PHY_INTERFACE_MODE_NA;
+ 
+ 	/* Enable and reset MIB counters */
+@@ -2365,10 +2376,6 @@ static void mt753x_phylink_mac_link_up(s
+ 	}
+ 	if (duplex == DUPLEX_FULL) {
+ 		mcr |= PMCR_FORCE_FDX;
+-		if (tx_pause)
+-			mcr |= PMCR_TX_FC_EN;
+-		if (rx_pause)
+-			mcr |= PMCR_RX_FC_EN;
+ 	}
+ 
+ 	if (mode == MLO_AN_PHY && phydev && phy_init_eee(phydev, 0) >= 0) {
+@@ -2476,9 +2483,6 @@ mt753x_phylink_validate(struct dsa_switc
+ 
+ 	priv->info->mac_port_validate(ds, port, mask);
+ 
+-	phylink_set(mask, Pause);
+-	phylink_set(mask, Asym_Pause);
+-
+ 	linkmode_and(supported, supported, mask);
+ 	linkmode_and(state->advertising, state->advertising, mask);
+ 
+@@ -2519,12 +2523,6 @@ mt7530_phylink_mac_link_state(struct dsa
+ 		break;
+ 	}
+ 
+-	state->pause &= ~(MLO_PAUSE_RX | MLO_PAUSE_TX);
+-	if (pmsr & PMSR_RX_FC)
+-		state->pause |= MLO_PAUSE_RX;
+-	if (pmsr & PMSR_TX_FC)
+-		state->pause |= MLO_PAUSE_TX;
+-
+ 	return 1;
+ }
+ 
+--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+@@ -398,12 +398,6 @@ static void mtk_mac_pcs_get_state(struct
+ 		state->speed = SPEED_UNKNOWN;
+ 		break;
+ 	}
+-
+-	state->pause &= (MLO_PAUSE_RX | MLO_PAUSE_TX);
+-	if (pmsr & MAC_MSR_RX_FC)
+-		state->pause |= MLO_PAUSE_RX;
+-	if (pmsr & MAC_MSR_TX_FC)
+-		state->pause |= MLO_PAUSE_TX;
+ }
+ 
+ static void mtk_mac_an_restart(struct phylink_config *config)
+@@ -434,9 +428,7 @@ static void mtk_mac_link_up(struct phyli
+ 					   phylink_config);
+ 	u32 mcr = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id));
+ 
+-	mcr &= ~(MAC_MCR_SPEED_100 | MAC_MCR_SPEED_1000 |
+-		 MAC_MCR_FORCE_DPX | MAC_MCR_FORCE_TX_FC |
+-		 MAC_MCR_FORCE_RX_FC);
++	mcr &= ~(MAC_MCR_SPEED_100 | MAC_MCR_SPEED_1000 | MAC_MCR_FORCE_DPX);
+ 
+ 	/* Configure speed */
+ 	switch (speed) {
+@@ -453,12 +445,6 @@ static void mtk_mac_link_up(struct phyli
+ 	if (duplex == DUPLEX_FULL)
+ 		mcr |= MAC_MCR_FORCE_DPX;
+ 
+-	/* Configure pause modes - phylink will avoid these for half duplex */
+-	if (tx_pause)
+-		mcr |= MAC_MCR_FORCE_TX_FC;
+-	if (rx_pause)
+-		mcr |= MAC_MCR_FORCE_RX_FC;
+-
+ 	mcr |= MAC_MCR_TX_EN | MAC_MCR_RX_EN;
+ 	mtk_w32(mac->hw, mcr, MTK_MAC_MCR(mac->id));
+ }
+@@ -537,9 +523,6 @@ static void mtk_validate(struct phylink_
+ 		}
+ 	}
+ 
+-	phylink_set(mask, Pause);
+-	phylink_set(mask, Asym_Pause);
+-
+ 	linkmode_and(supported, supported, mask);
+ 	linkmode_and(state->advertising, state->advertising, mask);
+