Use a pyVHDLModel to extract implementation info

The interface to VHDL files should use pyVHDLModel:

• https://github.com/VHDL/pyVHDLModel
• We could either:
  • Defer the creation of this model to GHDL:
    • https://vhdl.github.io/pyVHDLModel/GettingStarted.html#ghdl-as-parser
    • This introduces the "awkward" dependency on GHDL.
    • This isn't awful, but we don't want people to have to build GHDL.
    • It's worth trying this in the first instance.
  • Create this model from the tree-sitter-vhdl parse.
    • This is quite a significant task, but will likely offer the quickest running solution.

This won't give us code editability, but that is a much longer term ambition.