Commit f31a2a76 authored by Biju Das's avatar Biju Das Committed by Nobuhiro Iwamatsu
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clk: renesas: rzg2l: Fix clk status function



commit fa2a30f8e0aa9304919750b116a9e9e322465299 upstream.

As per RZ/G2L HW(Rev.0.50) manual, clock monitor register value
0 means clock is not supplied and 1 means clock is supplied.
This patch fixes the issue by removing the inverted logic.

Fixing the above, triggered following 2 issues

1) GIC interrupts don't work if we disable IA55_CLK and DMAC_ACLK.
   Fixed this issue by adding these clocks as critical clocks.

2) DMA is not working, since the DMA driver is not turning on DMAC_PCLK.
   So will provide a fix in the DMA driver to turn on DMA_PCLK.

Fixes: ef3c613ccd68 ("clk: renesas: Add CPG core wrapper for RZ/G2L SoC")
Signed-off-by: default avatarBiju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20210922112405.26413-2-biju.das.jz@bp.renesas.com

Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: default avatarLad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20211216125446.15451-25-prabhakar.mahadev-lad.rj@bp.renesas.com

Signed-off-by: Nobuhiro Iwamatsu's avatarNobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>
parent 2dda7a20
Pipeline #431663140 passed with stages
in 258 minutes and 26 seconds
......@@ -451,7 +451,7 @@ static int rzg2l_mod_clock_is_enabled(struct clk_hw *hw)
value = readl(priv->base + CLK_MON_R(clock->off));
return !(value & bitmask);
return value & bitmask;
}
static const struct clk_ops rzg2l_mod_clock_ops = {
......
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