Commit 9b963e5d authored by David S. Miller's avatar David S. Miller

Merge branch 'master' of master.kernel.org:/pub/scm/linux/kernel/git/davem/net-2.6

Conflicts:
	drivers/ieee802154/fakehard.c
	drivers/net/e1000e/ich8lan.c
	drivers/net/e1000e/phy.c
	drivers/net/netxen/netxen_nic_init.c
	drivers/net/wireless/ath/ath9k/main.c
parents 3b8626ba 5fdd4bae
......@@ -284,13 +284,13 @@ static netdev_tx_t ieee802154_fake_xmit(struct sk_buff *skb,
{
skb->skb_iif = dev->ifindex;
skb->dev = dev;
dev->stats.tx_packets++;
dev->stats.tx_bytes += skb->len;
dev->trans_start = jiffies;
/* FIXME: do hardware work here ... */
dev_kfree_skb(skb);
return NETDEV_TX_OK;
}
......
......@@ -975,7 +975,7 @@ config ENC28J60_WRITEVERIFY
config ETHOC
tristate "OpenCores 10/100 Mbps Ethernet MAC support"
depends on NET_ETHERNET && HAS_IOMEM
depends on NET_ETHERNET && HAS_IOMEM && HAS_DMA
select MII
select PHYLIB
select CRC32
......
......@@ -1088,7 +1088,14 @@ static struct net_device * au1000_probe(int port_num)
return NULL;
}
if ((err = register_netdev(dev)) != 0) {
dev->base_addr = base;
dev->irq = irq;
dev->netdev_ops = &au1000_netdev_ops;
SET_ETHTOOL_OPS(dev, &au1000_ethtool_ops);
dev->watchdog_timeo = ETH_TX_TIMEOUT;
err = register_netdev(dev);
if (err != 0) {
printk(KERN_ERR "%s: Cannot register net device, error %d\n",
DRV_NAME, err);
free_netdev(dev);
......@@ -1209,12 +1216,6 @@ static struct net_device * au1000_probe(int port_num)
aup->tx_db_inuse[i] = pDB;
}
dev->base_addr = base;
dev->irq = irq;
dev->netdev_ops = &au1000_netdev_ops;
SET_ETHTOOL_OPS(dev, &au1000_ethtool_ops);
dev->watchdog_timeo = ETH_TX_TIMEOUT;
/*
* The boot code uses the ethernet controller, so reset it to start
* fresh. au1000_init() expects that the device is in reset state.
......
......@@ -142,6 +142,8 @@ struct e1000_info;
#define HV_TNCRS_UPPER PHY_REG(778, 29) /* Transmit with no CRS */
#define HV_TNCRS_LOWER PHY_REG(778, 30)
#define E1000_FCRTV_PCH 0x05F40 /* PCH Flow Control Refresh Timer Value */
/* BM PHY Copper Specific Status */
#define BM_CS_STATUS 17
#define BM_CS_STATUS_LINK_UP 0x0400
......
......@@ -1110,7 +1110,8 @@ static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state)
oem_reg |= HV_OEM_BITS_LPLU;
}
/* Restart auto-neg to activate the bits */
oem_reg |= HV_OEM_BITS_RESTART_AN;
if (!e1000_check_reset_block(hw))
oem_reg |= HV_OEM_BITS_RESTART_AN;
ret_val = hw->phy.ops.write_reg_locked(hw, HV_OEM_BITS, oem_reg);
out:
......@@ -3545,6 +3546,7 @@ struct e1000_info e1000_pch_info = {
| FLAG_HAS_AMT
| FLAG_HAS_FLASH
| FLAG_HAS_JUMBO_FRAMES
| FLAG_DISABLE_FC_PAUSE_TIME /* errata */
| FLAG_APME_IN_WUC,
.pba = 26,
.max_hw_frame_size = 4096,
......
......@@ -2760,25 +2760,38 @@ void e1000e_reset(struct e1000_adapter *adapter)
/*
* flow control settings
*
* The high water mark must be low enough to fit two full frame
* The high water mark must be low enough to fit one full frame
* (or the size used for early receive) above it in the Rx FIFO.
* Set it to the lower of:
* - 90% of the Rx FIFO size, and
* - the full Rx FIFO size minus the early receive size (for parts
* with ERT support assuming ERT set to E1000_ERT_2048), or
* - the full Rx FIFO size minus two full frames
* - the full Rx FIFO size minus one full frame
*/
if ((adapter->flags & FLAG_HAS_ERT) &&
(adapter->netdev->mtu > ETH_DATA_LEN))
hwm = min(((pba << 10) * 9 / 10),
((pba << 10) - (E1000_ERT_2048 << 3)));
else
hwm = min(((pba << 10) * 9 / 10),
((pba << 10) - (2 * adapter->max_frame_size)));
if (hw->mac.type == e1000_pchlan) {
/*
* Workaround PCH LOM adapter hangs with certain network
* loads. If hangs persist, try disabling Tx flow control.
*/
if (adapter->netdev->mtu > ETH_DATA_LEN) {
fc->high_water = 0x3500;
fc->low_water = 0x1500;
} else {
fc->high_water = 0x5000;
fc->low_water = 0x3000;
}
} else {
if ((adapter->flags & FLAG_HAS_ERT) &&
(adapter->netdev->mtu > ETH_DATA_LEN))
hwm = min(((pba << 10) * 9 / 10),
((pba << 10) - (E1000_ERT_2048 << 3)));
else
hwm = min(((pba << 10) * 9 / 10),
((pba << 10) - adapter->max_frame_size));
fc->high_water = hwm & E1000_FCRTH_RTH; /* 8-byte granularity */
fc->low_water = (fc->high_water - (2 * adapter->max_frame_size));
fc->low_water &= E1000_FCRTL_RTL; /* 8-byte granularity */
fc->high_water = hwm & E1000_FCRTH_RTH; /* 8-byte granularity */
fc->low_water = fc->high_water - 8;
}
if (adapter->flags & FLAG_DISABLE_FC_PAUSE_TIME)
fc->pause_time = 0xFFFF;
......@@ -2804,6 +2817,10 @@ void e1000e_reset(struct e1000_adapter *adapter)
if (mac->ops.init_hw(hw))
e_err("Hardware Error\n");
/* additional part of the flow-control workaround above */
if (hw->mac.type == e1000_pchlan)
ew32(FCRTV_PCH, 0x1000);
e1000_update_mng_vlan(adapter);
/* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
......@@ -3612,7 +3629,7 @@ static void e1000_watchdog_task(struct work_struct *work)
case SPEED_100:
txb2b = 0;
netdev->tx_queue_len = 100;
/* maybe add some timeout factor ? */
adapter->tx_timeout_factor = 10;
break;
}
......@@ -4284,8 +4301,10 @@ static int e1000_change_mtu(struct net_device *netdev, int new_mtu)
while (test_and_set_bit(__E1000_RESETTING, &adapter->state))
msleep(1);
/* e1000e_down has a dependency on max_frame_size */
/* e1000e_down -> e1000e_reset dependent on max_frame_size & mtu */
adapter->max_frame_size = max_frame;
e_info("changing MTU from %d to %d\n", netdev->mtu, new_mtu);
netdev->mtu = new_mtu;
if (netif_running(netdev))
e1000e_down(adapter);
......@@ -4315,9 +4334,6 @@ static int e1000_change_mtu(struct net_device *netdev, int new_mtu)
adapter->rx_buffer_len = ETH_FRAME_LEN + VLAN_HLEN
+ ETH_FCS_LEN;
e_info("changing MTU from %d to %d\n", netdev->mtu, new_mtu);
netdev->mtu = new_mtu;
if (netif_running(netdev))
e1000e_up(adapter);
else
......
......@@ -71,7 +71,6 @@ static const u16 e1000_igp_2_cable_length_table[] =
#define I82577_CFG_ASSERT_CRS_ON_TX (1 << 15)
#define I82577_CFG_ENABLE_DOWNSHIFT (3 << 10) /* auto downshift 100/10 */
#define I82577_CTRL_REG 23
#define I82577_CTRL_DOWNSHIFT_MASK (7 << 10)
/* 82577 specific PHY registers */
#define I82577_PHY_CTRL_2 18
......@@ -660,15 +659,6 @@ s32 e1000_copper_link_setup_82577(struct e1000_hw *hw)
phy_data |= I82577_CFG_ENABLE_DOWNSHIFT;
ret_val = phy->ops.write_reg(hw, I82577_CFG_REG, phy_data);
if (ret_val)
goto out;
/* Set number of link attempts before downshift */
ret_val = phy->ops.read_reg(hw, I82577_CTRL_REG, &phy_data);
if (ret_val)
goto out;
phy_data &= ~I82577_CTRL_DOWNSHIFT_MASK;
ret_val = phy->ops.write_reg(hw, I82577_CTRL_REG, phy_data);
out:
return ret_val;
......@@ -2658,19 +2648,18 @@ static s32 __e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data,
page = 0;
if (reg > MAX_PHY_MULTI_PAGE_REG) {
if ((hw->phy.type != e1000_phy_82578) ||
((reg != I82578_ADDR_REG) &&
(reg != I82578_ADDR_REG + 1))) {
u32 phy_addr = hw->phy.addr;
u32 phy_addr = hw->phy.addr;
hw->phy.addr = 1;
hw->phy.addr = 1;
/* Page is shifted left, PHY expects (page x 32) */
ret_val = e1000e_write_phy_reg_mdic(hw,
IGP01E1000_PHY_PAGE_SELECT,
(page << IGP_PAGE_SHIFT));
hw->phy.addr = phy_addr;
}
/* Page is shifted left, PHY expects (page x 32) */
ret_val = e1000e_write_phy_reg_mdic(hw,
IGP01E1000_PHY_PAGE_SELECT,
(page << IGP_PAGE_SHIFT));
hw->phy.addr = phy_addr;
if (ret_val)
goto out;
}
ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg,
......@@ -2678,7 +2667,7 @@ static s32 __e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data,
out:
/* Revert to MDIO fast mode, if applicable */
if ((hw->phy.type == e1000_phy_82577) && in_slow_mode)
ret_val = e1000_set_mdio_slow_mode_hv(hw, false);
ret_val |= e1000_set_mdio_slow_mode_hv(hw, false);
if (!locked)
hw->phy.ops.release(hw);
......@@ -2784,19 +2773,18 @@ static s32 __e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data,
}
if (reg > MAX_PHY_MULTI_PAGE_REG) {
if ((hw->phy.type != e1000_phy_82578) ||
((reg != I82578_ADDR_REG) &&
(reg != I82578_ADDR_REG + 1))) {
u32 phy_addr = hw->phy.addr;
u32 phy_addr = hw->phy.addr;
hw->phy.addr = 1;
hw->phy.addr = 1;
/* Page is shifted left, PHY expects (page x 32) */
ret_val = e1000e_write_phy_reg_mdic(hw,
IGP01E1000_PHY_PAGE_SELECT,
(page << IGP_PAGE_SHIFT));
hw->phy.addr = phy_addr;
}
/* Page is shifted left, PHY expects (page x 32) */
ret_val = e1000e_write_phy_reg_mdic(hw,
IGP01E1000_PHY_PAGE_SELECT,
(page << IGP_PAGE_SHIFT));
hw->phy.addr = phy_addr;
if (ret_val)
goto out;
}
ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg,
......@@ -2805,7 +2793,7 @@ static s32 __e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data,
out:
/* Revert to MDIO fast mode, if applicable */
if ((hw->phy.type == e1000_phy_82577) && in_slow_mode)
ret_val = e1000_set_mdio_slow_mode_hv(hw, false);
ret_val |= e1000_set_mdio_slow_mode_hv(hw, false);
if (!locked)
hw->phy.ops.release(hw);
......
......@@ -242,11 +242,11 @@ static void ixgbe_unmap_and_free_tx_resource(struct ixgbe_adapter *adapter,
static inline bool ixgbe_tx_is_paused(struct ixgbe_adapter *adapter,
struct ixgbe_ring *tx_ring)
{
int tc;
u32 txoff = IXGBE_TFCS_TXOFF;
#ifdef CONFIG_IXGBE_DCB
if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
int tc;
int reg_idx = tx_ring->reg_idx;
int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
......
......@@ -568,6 +568,16 @@ static inline void ks_outblk(struct ks_net *ks, u16 *wptr, u32 len)
iowrite16(*wptr++, ks->hw_addr);
}
static void ks_disable_int(struct ks_net *ks)
{
ks_wrreg16(ks, KS_IER, 0x0000);
} /* ks_disable_int */
static void ks_enable_int(struct ks_net *ks)
{
ks_wrreg16(ks, KS_IER, ks->rc_ier);
} /* ks_enable_int */
/**
* ks_tx_fifo_space - return the available hardware buffer size.
* @ks: The chip information
......@@ -681,6 +691,47 @@ static void ks_soft_reset(struct ks_net *ks, unsigned op)
}
void ks_enable_qmu(struct ks_net *ks)
{
u16 w;
w = ks_rdreg16(ks, KS_TXCR);
/* Enables QMU Transmit (TXCR). */
ks_wrreg16(ks, KS_TXCR, w | TXCR_TXE);
/*
* RX Frame Count Threshold Enable and Auto-Dequeue RXQ Frame
* Enable
*/
w = ks_rdreg16(ks, KS_RXQCR);
ks_wrreg16(ks, KS_RXQCR, w | RXQCR_RXFCTE);
/* Enables QMU Receive (RXCR1). */
w = ks_rdreg16(ks, KS_RXCR1);
ks_wrreg16(ks, KS_RXCR1, w | RXCR1_RXE);
ks->enabled = true;
} /* ks_enable_qmu */
static void ks_disable_qmu(struct ks_net *ks)
{
u16 w;
w = ks_rdreg16(ks, KS_TXCR);
/* Disables QMU Transmit (TXCR). */
w &= ~TXCR_TXE;
ks_wrreg16(ks, KS_TXCR, w);
/* Disables QMU Receive (RXCR1). */
w = ks_rdreg16(ks, KS_RXCR1);
w &= ~RXCR1_RXE ;
ks_wrreg16(ks, KS_RXCR1, w);
ks->enabled = false;
} /* ks_disable_qmu */
/**
* ks_read_qmu - read 1 pkt data from the QMU.
* @ks: The chip information
......@@ -752,7 +803,7 @@ static void ks_rcv(struct ks_net *ks, struct net_device *netdev)
(frame_hdr->len < RX_BUF_SIZE) && frame_hdr->len)) {
skb_reserve(skb, 2);
/* read data block including CRC 4 bytes */
ks_read_qmu(ks, (u16 *)skb->data, frame_hdr->len + 4);
ks_read_qmu(ks, (u16 *)skb->data, frame_hdr->len);
skb_put(skb, frame_hdr->len);
skb->dev = netdev;
skb->protocol = eth_type_trans(skb, netdev);
......@@ -861,7 +912,7 @@ static int ks_net_open(struct net_device *netdev)
ks_dbg(ks, "%s - entry\n", __func__);
/* reset the HW */
err = request_irq(ks->irq, ks_irq, KS_INT_FLAGS, DRV_NAME, ks);
err = request_irq(ks->irq, ks_irq, KS_INT_FLAGS, DRV_NAME, netdev);
if (err) {
printk(KERN_ERR "Failed to request IRQ: %d: %d\n",
......@@ -869,6 +920,15 @@ static int ks_net_open(struct net_device *netdev)
return err;
}
/* wake up powermode to normal mode */
ks_set_powermode(ks, PMECR_PM_NORMAL);
mdelay(1); /* wait for normal mode to take effect */
ks_wrreg16(ks, KS_ISR, 0xffff);
ks_enable_int(ks);
ks_enable_qmu(ks);
netif_start_queue(ks->netdev);
if (netif_msg_ifup(ks))
ks_dbg(ks, "network device %s up\n", netdev->name);
......@@ -892,19 +952,14 @@ static int ks_net_stop(struct net_device *netdev)
netif_stop_queue(netdev);
kfree(ks->frame_head_info);
mutex_lock(&ks->lock);
/* turn off the IRQs and ack any outstanding */
ks_wrreg16(ks, KS_IER, 0x0000);
ks_wrreg16(ks, KS_ISR, 0xffff);
/* shutdown RX process */
ks_wrreg16(ks, KS_RXCR1, 0x0000);
/* shutdown TX process */
ks_wrreg16(ks, KS_TXCR, 0x0000);
/* shutdown RX/TX QMU */
ks_disable_qmu(ks);
/* set powermode to soft power down to save power */
ks_set_powermode(ks, PMECR_PM_SOFTDOWN);
......@@ -929,17 +984,8 @@ static int ks_net_stop(struct net_device *netdev)
*/
static void ks_write_qmu(struct ks_net *ks, u8 *pdata, u16 len)
{
unsigned fid = ks->fid;
fid = ks->fid;
ks->fid = (ks->fid + 1) & TXFR_TXFID_MASK;
/* reduce the tx interrupt occurrances. */
if (!fid)
fid |= TXFR_TXIC; /* irq on completion */
/* start header at txb[0] to align txw entries */
ks->txh.txw[0] = cpu_to_le16(fid);
ks->txh.txw[0] = 0;
ks->txh.txw[1] = cpu_to_le16(len);
/* 1. set sudo-DMA mode */
......@@ -957,16 +1003,6 @@ static void ks_write_qmu(struct ks_net *ks, u8 *pdata, u16 len)
;
}
static void ks_disable_int(struct ks_net *ks)
{
ks_wrreg16(ks, KS_IER, 0x0000);
} /* ks_disable_int */
static void ks_enable_int(struct ks_net *ks)
{
ks_wrreg16(ks, KS_IER, ks->rc_ier);
} /* ks_enable_int */
/**
* ks_start_xmit - transmit packet
* @skb : The buffer to transmit
......@@ -1410,25 +1446,6 @@ static int ks_read_selftest(struct ks_net *ks)
return ret;
}
static void ks_disable(struct ks_net *ks)
{
u16 w;
w = ks_rdreg16(ks, KS_TXCR);
/* Disables QMU Transmit (TXCR). */
w &= ~TXCR_TXE;
ks_wrreg16(ks, KS_TXCR, w);
/* Disables QMU Receive (RXCR1). */
w = ks_rdreg16(ks, KS_RXCR1);
w &= ~RXCR1_RXE ;
ks_wrreg16(ks, KS_RXCR1, w);
ks->enabled = false;
} /* ks_disable */
static void ks_setup(struct ks_net *ks)
{
u16 w;
......@@ -1463,7 +1480,7 @@ static void ks_setup(struct ks_net *ks)
w = TXCR_TXFCE | TXCR_TXPE | TXCR_TXCRC | TXCR_TCGIP;
ks_wrreg16(ks, KS_TXCR, w);
w = RXCR1_RXFCE | RXCR1_RXBE | RXCR1_RXUE;
w = RXCR1_RXFCE | RXCR1_RXBE | RXCR1_RXUE | RXCR1_RXME | RXCR1_RXIPFCC;
if (ks->promiscuous) /* bPromiscuous */
w |= (RXCR1_RXAE | RXCR1_RXINVF);
......@@ -1486,28 +1503,6 @@ static void ks_setup_int(struct ks_net *ks)
ks->rc_ier = (IRQ_LCI | IRQ_TXI | IRQ_RXI);
} /* ks_setup_int */
void ks_enable(struct ks_net *ks)
{
u16 w;
w = ks_rdreg16(ks, KS_TXCR);
/* Enables QMU Transmit (TXCR). */
ks_wrreg16(ks, KS_TXCR, w | TXCR_TXE);
/*
* RX Frame Count Threshold Enable and Auto-Dequeue RXQ Frame
* Enable
*/
w = ks_rdreg16(ks, KS_RXQCR);
ks_wrreg16(ks, KS_RXQCR, w | RXQCR_RXFCTE);
/* Enables QMU Receive (RXCR1). */
w = ks_rdreg16(ks, KS_RXCR1);
ks_wrreg16(ks, KS_RXCR1, w | RXCR1_RXE);
ks->enabled = true;
} /* ks_enable */
static int ks_hw_init(struct ks_net *ks)
{
#define MHEADER_SIZE (sizeof(struct type_frame_head) * MAX_RECV_FRAMES)
......@@ -1612,11 +1607,9 @@ static int __devinit ks8851_probe(struct platform_device *pdev)
ks_soft_reset(ks, GRR_GSR);
ks_hw_init(ks);
ks_disable(ks);
ks_disable_qmu(ks);
ks_setup(ks);
ks_setup_int(ks);
ks_enable_int(ks);
ks_enable(ks);
memcpy(netdev->dev_addr, ks->mac_addr, 6);
data = ks_rdreg16(ks, KS_OBCR);
......@@ -1658,6 +1651,7 @@ static int __devexit ks8851_remove(struct platform_device *pdev)
struct ks_net *ks = netdev_priv(netdev);
struct resource *iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
kfree(ks->frame_head_info);
unregister_netdev(netdev);
iounmap(ks->hw_addr);
free_netdev(netdev);
......
......@@ -446,6 +446,7 @@ static int macvlan_init(struct net_device *dev)
dev->state = (dev->state & ~MACVLAN_STATE_MASK) |
(lowerdev->state & MACVLAN_STATE_MASK);
dev->features = lowerdev->features & MACVLAN_FEATURES;
dev->gso_max_size = lowerdev->gso_max_size;
dev->iflink = lowerdev->ifindex;
dev->hard_header_len = lowerdev->hard_header_len;
......@@ -772,6 +773,7 @@ static int macvlan_device_event(struct notifier_block *unused,
case NETDEV_FEAT_CHANGE:
list_for_each_entry(vlan, &port->vlans, list) {
vlan->dev->features = dev->features & MACVLAN_FEATURES;
vlan->dev->gso_max_size = dev->gso_max_size;
netdev_features_change(vlan->dev);
}
break;
......
......@@ -1202,6 +1202,8 @@ struct netxen_adapter {
u32 int_vec_bit;
u32 heartbit;
u8 mac_addr[ETH_ALEN];
struct netxen_adapter_stats stats;
struct netxen_recv_context recv_ctx;
......
......@@ -545,6 +545,8 @@ enum {
#define NETXEN_NIU_TEST_MUX_CTL (NETXEN_CRB_NIU + 0x00094)
#define NETXEN_NIU_XG_PAUSE_CTL (NETXEN_CRB_NIU + 0x00098)
#define NETXEN_NIU_XG_PAUSE_LEVEL (NETXEN_CRB_NIU + 0x000dc)
#define NETXEN_NIU_FRAME_COUNT_SELECT (NETXEN_CRB_NIU + 0x000ac)
#define NETXEN_NIU_FRAME_COUNT (NETXEN_CRB_NIU + 0x000b0)
#define NETXEN_NIU_XG_SEL (NETXEN_CRB_NIU + 0x00128)
#define NETXEN_NIU_GB_PAUSE_CTL (NETXEN_CRB_NIU + 0x0030c)
......
......@@ -389,24 +389,51 @@ int netxen_niu_disable_xg_port(struct netxen_adapter *adapter)
int netxen_p2_nic_set_promisc(struct netxen_adapter *adapter, u32 mode)
{
__u32 reg;
u32 mac_cfg;
u32 cnt = 0;
__u32 reg = 0x0200;
u32 port = adapter->physical_port;
u16 board_type = adapter->ahw.board_type;
if (port > NETXEN_NIU_MAX_XG_PORTS)
return -EINVAL;
reg = NXRD32(adapter, NETXEN_NIU_XGE_CONFIG_1 + (0x10000 * port));
if (mode == NETXEN_NIU_PROMISC_MODE)
reg = (reg | 0x2000UL);
else
reg = (reg & ~0x2000UL);
mac_cfg = NXRD32(adapter, NETXEN_NIU_XGE_CONFIG_0 + (0x10000 * port));
mac_cfg &= ~0x4;
NXWR32(adapter, NETXEN_NIU_XGE_CONFIG_0 + (0x10000 * port), mac_cfg);
if (mode == NETXEN_NIU_ALLMULTI_MODE)
reg = (reg | 0x1000UL);
else
reg = (reg & ~0x1000UL);
if ((board_type == NETXEN_BRDTYPE_P2_SB31_10G_IMEZ) ||
(board_type == NETXEN_BRDTYPE_P2_SB31_10G_HMEZ))
reg = (0x20 << port);
NXWR32(adapter, NETXEN_NIU_FRAME_COUNT_SELECT, reg);
mdelay(10);
while (NXRD32(adapter, NETXEN_NIU_FRAME_COUNT) && ++cnt < 20)
mdelay(10);
if (cnt < 20) {
reg = NXRD32(adapter,
NETXEN_NIU_XGE_CONFIG_1 + (0x10000 * port));
if (mode == NETXEN_NIU_PROMISC_MODE)
reg = (reg | 0x2000UL);
else
reg = (reg & ~0x2000UL);
if (mode == NETXEN_NIU_ALLMULTI_MODE)
reg = (reg | 0x1000UL);
else
reg = (reg & ~0x1000UL);
NXWR32(adapter,
NETXEN_NIU_XGE_CONFIG_1 + (0x10000 * port), reg);
}
NXWR32(adapter, NETXEN_NIU_XGE_CONFIG_1 + (0x10000 * port), reg);
mac_cfg |= 0x4;
NXWR32(adapter, NETXEN_NIU_XGE_CONFIG_0 + (0x10000 * port), mac_cfg);
return 0;
}
......@@ -442,7 +469,7 @@ netxen_nic_enable_mcast_filter(struct netxen_adapter *adapter)
{
u32 val = 0;
u16 port = adapter->physical_port;
u8 *addr = adapter->netdev->dev_addr;
u8 *addr = adapter->mac_addr;
if (adapter->mc_enabled)
return 0;
......@@ -471,7 +498,7 @@ netxen_nic_disable_mcast_filter(struct netxen_adapter *adapter)
{
u32 val = 0;
u16 port = adapter->physical_port;
u8 *addr = adapter->netdev->dev_addr;
u8 *addr = adapter->mac_addr;
if (!adapter->mc_enabled)
return 0;
......@@ -666,7 +693,7 @@ void netxen_p3_nic_set_multi(struct net_device *netdev)
list_splice_tail_init(&adapter->mac_list, &del_list);
nx_p3_nic_add_mac(adapter, netdev->dev_addr, &del_list);
nx_p3_nic_add_mac(adapter, adapter->mac_addr, &del_list);
nx_p3_nic_add_mac(adapter, bcast_addr, &del_list);
if (netdev->flags & IFF_PROMISC) {
......
......@@ -445,6 +445,7 @@ netxen_read_mac_addr(struct netxen_adapter *adapter)
netdev->dev_addr[i] = *(p + 5 - i);
memcpy(netdev->perm_addr, netdev->dev_addr, netdev->addr_len);
memcpy(adapter->mac_addr, netdev->dev_addr, netdev->addr_len);
/* set station address */
......@@ -467,6 +468,7 @@ int netxen_nic_set_mac(struct net_device *netdev, void *p)
netxen_napi_disable(adapter);
}
memcpy(adapter->mac_addr, addr->sa_data, netdev->addr_len);
memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
adapter->macaddr_set(adapter, addr->sa_data);
......@@ -960,7 +962,7 @@ netxen_nic_up(struct netxen_adapter *adapter, struct net_device *netdev)
return err;
}
if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
adapter->macaddr_set(adapter, netdev->dev_addr);
adapter->macaddr_set(adapter, adapter->mac_addr);
adapter->set_multi(netdev);
adapter->set_mtu(adapter, netdev->mtu);
......
......@@ -416,13 +416,8 @@ static void init_dma_desc_rings(struct net_device *dev)
unsigned int txsize = priv->dma_tx_size;
unsigned int rxsize = priv->dma_rx_size;
unsigned int bfsize = priv->dma_buf_sz;
int buff2_needed = 0;
int dis_ic = 0;
int buff2_needed = 0, dis_ic = 0;
#ifdef CONFIG_STMMAC_TIMER
/* Using Timers disable interrupts on completion for the reception */
dis_ic = 1;
#endif
/* Set the Buffer size according to the MTU;
* indeed, in case of jumbo we need to bump-up the buffer sizes.
*/
......@@ -437,6 +432,11 @@ static void init_dma_desc_rings(struct net_device *dev)
else
bfsize = DMA_BUFFER_SIZE;
#ifdef CONFIG_STMMAC_TIMER
/* Disable interrupts on completion for the reception if timer is on */
if (likely(priv->tm->enable))
dis_ic = 1;
#endif
/* If the MTU exceeds 8k so use the second buffer in the chain */
if (bfsize >= BUF_SIZE_8KiB)
buff2_needed = 1;
......@@ -809,20 +809,22 @@ static void stmmac_tx(struct stmmac_priv *priv)
static inline void stmmac_enable_irq(struct stmmac_priv *priv)
{
#ifndef CONFIG_STMMAC_TIMER
writel(DMA_INTR_DEFAULT_MASK, priv->dev->base_addr + DMA_INTR_ENA);
#else
priv->tm->timer_start(tmrate);
#ifdef CONFIG_STMMAC_TIMER
if (likely(priv->tm->enable))
priv->tm->timer_start(tmrate);
else
#endif
writel(DMA_INTR_DEFAULT_MASK, priv->dev->base_addr + DMA_INTR_ENA);
}
static inline void stmmac_disable_irq(struct stmmac_priv *priv)
{
#ifndef CONFIG_STMMAC_TIMER
writel(0, priv->dev->base_addr +