Issues · ChipEleven / pythonwatt · GitLab

Convert regfile to be able to use BRAMs

#18 · opened Dec 16, 2020 by Michael Nolan timing_issue
- CLOSED
- 0
updated Jan 09, 2021
Pipeline popcnt instruction

#13 · opened Dec 14, 2020 by Michael Nolan timing_issue
- CLOSED
- 1
- 0
updated Dec 23, 2020
Investigate using sqlite or other sql database for decoder info

#4 · opened Aug 25, 2020 by Michael Nolan
- CLOSED
- 1
- 0
updated Dec 20, 2020
Rework Fetch stage so it issues an average of 1 instruction/cycle

#17 · opened Dec 16, 2020 by Michael Nolan
- CLOSED
- 1
- 0
updated Dec 16, 2020
Make ministage class from execute stage into nmigen modules

#12 · opened Dec 14, 2020 by Michael Nolan Doing timing_issue
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- 1
- 0
updated Dec 15, 2020
AXI_Ram module doesn't get mapped to a BRAM during synthesis

#14 · opened Dec 14, 2020 by Michael Nolan bug
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- 1
- 0
updated Dec 14, 2020
Nmien update breaks union.py

#11 · opened Nov 07, 2020 by Michael Nolan hello world bug
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- 1
- 0
updated Nov 07, 2020
Add ability to write two registers with one instruction

#7 · opened Sep 28, 2020 by Michael Nolan hello world
- CLOSED
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updated Nov 05, 2020
BUG: regfile read_stage doesn't invalidate register use from speculative writes (that never complete)

#10 · opened Oct 07, 2020 by Michael Nolan bug
- CLOSED
- 1
updated Nov 05, 2020
Add SPRS and connect to branch unit

#6 · opened Sep 28, 2020 by Michael Nolan hello world
- CLOSED
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updated Nov 05, 2020
Create an env.py to do things like holding the name of the powerpc assembler

#3 · opened Aug 15, 2020 by Michael Nolan
- CLOSED
- 0
updated Aug 15, 2020
Move all unit tests to test folder under project root

#2 · opened Aug 15, 2020 by Michael Nolan
- CLOSED
- 0
updated Aug 15, 2020