Verified Commit 6f7b0d6a authored by betseg's avatar betseg 🏳🌈

fmt

parent 345fd632
156 ORE => 6 TLFQZ
1 SZFV => 5 TNXGD
1 BQLJ, 3 VNKPF => 8 BQXZ
43 FPRFS, 5 CQJT, 20 LDKTQ, 48 ZPBLH, 21 MFVG, 43 WLWZQ, 1 ZWZQ, 11 PQZJP, 56 CTJGD, 35 SGDVW => 1 FUEL
11 BQXZ, 1 PRCSN => 7 DVFD
7 VWXB, 2 PRCSN, 24 VJSR, 9 MDWCG, 4 MFVG => 4 ZWZQ
32 BQXZ, 5 XDSHP, 16 KTXJR, 7 VJSR, 3 MDWCG, 11 KZFZG, 3 NVBN => 5 ZPBLH
2 BQLJ, 2 RSKH, 3 VWXB => 2 GWXCF
6 PRCSN, 1 NCRZ => 8 VJSR
5 TMQLD => 9 VDQL
9 MZQZS, 1 FLRB => 5 BQLJ
4 KLHS => 5 PQZJP
1 WJTS, 1 NCRZ, 27 XDSHP => 8 MFVG
1 FNXMV, 30 FPKM => 8 RDMDL
1 TNXGD, 21 XBCLW, 5 CWNV => 3 RSKH
4 KQFPJ => 2 NCRZ
10 CWNV, 8 HSXW => 9 FNXMV
2 TNXGD, 4 CWNV, 13 VJSR => 8 KTXJR
3 NCRZ, 1 GWXCF, 8 NVBN, 6 MDWCG, 3 VWXB, 4 KTXJR, 4 DVFD, 3 QXCV => 9 FPRFS
5 MZQZS, 9 TBVRN => 7 SZFV
37 GWXCF, 15 RDMDL, 2 MDWCG => 7 CQJT
1 VDQL, 2 HSXW => 4 NVBN
18 QHMTL, 7 FLRB, 1 SZFV => 3 FPKM
6 VDQL => 1 FNCN
3 QPHT => 7 LDKTQ
1 TLFQZ => 8 FWFR
7 VDQL, 8 KZFZG => 3 HSXW
9 TBVRN => 7 MZQZS
1 FLRB, 44 VNKPF, 1 LVZF => 8 QXCV
1 WLWZQ, 3 TBVRN, 4 TLFQZ => 9 KQFPJ
1 BQLJ, 1 PRCSN, 8 DHTNG => 5 VWXB
1 XDSHP, 6 NVBN => 1 BDGC
8 PRCSN, 1 DHTNG => 2 WJTS
19 DHTNG, 22 WLWZQ => 9 LVZF
185 ORE => 7 WLWZQ
1 TMQLD, 1 MZQZS => 8 KZFZG
111 ORE => 4 TBVRN
31 VDQL, 14 MZQZS => 7 XBCLW
6 VDQL, 3 KVPK => 9 SGDVW
1 FNCN => 6 QMKT
1 FNCN, 3 TMQLD => 7 VNKPF
2 QPHT => 6 VQXCJ
2 LDKTQ, 3 VQXCJ => 5 FLRB
1 FNCN, 3 FPKM, 1 SZFV => 2 DHTNG
1 KZFZG => 9 QHMTL
141 ORE => 5 QPHT
16 TNXGD => 9 CWNV
1 KQFPJ, 29 FWFR => 2 KVPK
1 TNXGD, 7 KLHS => 2 XDSHP
7 WJTS => 6 MDWCG
3 BDGC, 3 XDSHP, 1 NCRZ => 4 CTJGD
3 QMKT => 6 PRCSN
24 FWFR => 2 TMQLD
8 VNKPF => 3 KLHS
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This diff is collapsed.
......@@ -61,7 +61,7 @@ type Tape = Vec<Cell>;
/// println!("received {}", mrx.recv().expect("VM disconnected."));
/// }
/// ```
#[derive(Debug)]
#[derive(Debug, Default)]
pub struct IntcodeVM {
tape: Tape,
ip: usize,
......@@ -72,20 +72,6 @@ pub struct IntcodeVM {
halted: bool,
}
impl Default for IntcodeVM {
fn default() -> Self {
Self {
tape: Vec::new(),
ip: 0,
rp: 0,
input: None,
output: None,
inp_wait_flag: None,
halted: false,
}
}
}
trait Flags {
fn flags(&self) -> (Mode, Mode, Mode);
}
......@@ -209,9 +195,7 @@ impl IntcodeVM {
self[loc] = self
.input
.as_ref()
.expect(
"Error: found input instruction but no receiver was created.",
)
.expect("Error: found input instruction but no receiver was created.")
.recv()
.expect("Error: failed to receive input: sender disconnected.");
self.ip += 2;
......@@ -222,9 +206,7 @@ impl IntcodeVM {
let val = self.get(one, 1);
self.output
.as_ref()
.expect(
"Error: found output instruction but no sender was created.",
)
.expect("Error: found output instruction but no sender was created.")
.send(val)
.expect("Error: failed to send output: receiver disconnected.");
self.ip += 2;
......
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