Commit 22f7eb86 authored by Arthur Carlsson's avatar Arthur Carlsson

Adapted the bitflags crate to new version

parent b7867d3b
Pipeline #15867227 failed with stage
in 6 minutes and 59 seconds
...@@ -4,6 +4,6 @@ version = "0.1.0" ...@@ -4,6 +4,6 @@ version = "0.1.0"
authors = ["Arthur Carlsson <arthur@kiron.net>"] authors = ["Arthur Carlsson <arthur@kiron.net>"]
[dependencies] [dependencies]
clap = "^2" clap = "2"
byteorder = "^1.2" byteorder = "1.2"
bitflags = "^1.0" bitflags = "1.0"
...@@ -17,10 +17,10 @@ impl Cpu { ...@@ -17,10 +17,10 @@ impl Cpu {
/// TODO: Maybe handle this as an exception which sets an exception bit? /// TODO: Maybe handle this as an exception which sets an exception bit?
pub fn power_on_reset(&mut self) { pub fn power_on_reset(&mut self) {
self.regs.pc = 0xFFFF_FFFF_BFC0_0000; self.regs.pc = 0xFFFF_FFFF_BFC0_0000;
self.regs.status -= reg::STATUS_DS_TS | reg::STATUS_DS_SR | reg::STATUS_RP; self.regs.status -= reg::Status::STATUS_DS_TS | reg::Status::STATUS_DS_SR | reg::Status::STATUS_RP;
self.regs.config -= reg::CONFIG_EP; self.regs.config -= reg::Config::CONFIG_EP;
self.regs.status |= reg::STATUS_ERL | reg::STATUS_DS_BEV; self.regs.status |= reg::Status::STATUS_ERL | reg::Status::STATUS_DS_BEV;
self.regs.config |= reg::CONFIG_BE; self.regs.config |= reg::Config::CONFIG_BE;
} }
/// Fetches the instruction for the current PC /// Fetches the instruction for the current PC
......
bitflags! { bitflags! {
/// Status registers as per "Figure 6-5 Status Register" in the datasheet /// Status registers as per "Figure 6-5 Status Register" in the datasheet
pub flags Status: u32 { pub struct Status: u32 {
const STATUS_IE = 1 << 0, const STATUS_IE = 1 << 0;
const STATUS_EXL = 1 << 1, const STATUS_EXL = 1 << 1;
const STATUS_ERL = 1 << 2, const STATUS_ERL = 1 << 2;
const STATUS_KSU = 0b11 << 3, const STATUS_KSU = 0b11 << 3;
const STATUS_UX = 1 << 5, const STATUS_UX = 1 << 5;
const STATUS_SX = 1 << 6, const STATUS_SX = 1 << 6;
const STATUS_KX = 1 << 7, const STATUS_KX = 1 << 7;
const STATUS_IM = 0b1111_1111 << 8, const STATUS_IM = 0b1111_1111 << 8;
const STATUS_DS_DE = 1 << 15, const STATUS_DS_DE = 1 << 15;
const STATUS_DS_CE = 1 << 16, const STATUS_DS_CE = 1 << 16;
const STATUS_DS_CH = 1 << 17, const STATUS_DS_CH = 1 << 17;
// ... 0 // ... 0
const STATUS_DS_SR = 1 << 19, const STATUS_DS_SR = 1 << 19;
const STATUS_DS_TS = 1 << 20, const STATUS_DS_TS = 1 << 20;
const STATUS_DS_BEV = 1 << 21, const STATUS_DS_BEV = 1 << 21;
// ... 0 // ... 0
const STATUS_DS_ITS = 1 << 23, const STATUS_DS_ITS = 1 << 23;
const STATUS_RE = 1 << 24, const STATUS_RE = 1 << 24;
const STATUS_FR = 1 << 25, const STATUS_FR = 1 << 25;
const STATUS_RP = 1 << 26, const STATUS_RP = 1 << 26;
const STATUS_CU = 0b1111 << 27, const STATUS_CU = 0b1111 << 27;
const STATUS_DS = STATUS_DS_DE.bits const STATUS_DS = Self::STATUS_DS_DE.bits
| STATUS_DS_CE.bits | Self::STATUS_DS_CE.bits
| STATUS_DS_CH.bits | Self::STATUS_DS_CH.bits
| STATUS_DS_SR.bits | Self::STATUS_DS_SR.bits
| STATUS_DS_TS.bits | Self::STATUS_DS_TS.bits
| STATUS_DS_BEV.bits | Self::STATUS_DS_BEV.bits
| STATUS_DS_ITS.bits, | Self::STATUS_DS_ITS.bits;
} }
} }
...@@ -38,27 +38,27 @@ bitflags! { ...@@ -38,27 +38,27 @@ bitflags! {
impl Status { impl Status {
/// Kernel mode segment as per "Table 5-4 64-Bit Kernel Mode Segments" /// Kernel mode segment as per "Table 5-4 64-Bit Kernel Mode Segments"
pub fn is_kernel_mode_address_segment(&self) -> bool { pub fn is_kernel_mode_address_segment(&self) -> bool {
(!self.contains(STATUS_KSU) || self.intersects(STATUS_EXL | STATUS_ERL)) (!self.contains(Status::STATUS_KSU) || self.intersects(Status::STATUS_EXL | Status::STATUS_ERL))
&& self.contains(STATUS_KX) && self.contains(Status::STATUS_KX)
} }
/// Supervisor mode segment as per "Table 5-2 32-Bit and 64-Bit Supervisor Mode Segments" /// Supervisor mode segment as per "Table 5-2 32-Bit and 64-Bit Supervisor Mode Segments"
pub fn is_supervisor_mode_address_segments(&self) -> bool { pub fn is_supervisor_mode_address_segments(&self) -> bool {
(*self & STATUS_KSU).bits == 0b01000 && !self.intersects(STATUS_EXL | STATUS_ERL) (*self & Status::STATUS_KSU).bits == 0b01000 && !self.intersects(Status::STATUS_EXL | Status::STATUS_ERL)
} }
} }
bitflags! { bitflags! {
/// Config register as per "Figure 5-16 Config Register" in the datasheet /// Config register as per "Figure 5-16 Config Register" in the datasheet
pub flags Config: u32 { pub struct Config: u32 {
const CONFIG_K0 = 0b111 << 0, const CONFIG_K0 = 0b111 << 0;
const CONFIG_CU = 1 << 3, const CONFIG_CU = 1 << 3;
// ... 1100100110 // ... 1100100110
const CONFIG_BE = 1 << 15, const CONFIG_BE = 1 << 15;
// ... 00000110 // ... 00000110
const CONFIG_EP = 0b1111 << 24, const CONFIG_EP = 0b1111 << 24;
const CONFIG_EC = 0b111 << 28, const CONFIG_EC = 0b111 << 28;
// ... 0 // ... 0
} }
...@@ -96,12 +96,11 @@ impl Default for Regs { ...@@ -96,12 +96,11 @@ impl Default for Regs {
#[cfg(test)] #[cfg(test)]
mod tests { mod tests {
use super::*; use super::*;
#[test] #[test]
fn test_is_kernel_mode_address_segment() { fn test_is_kernel_mode_address_segment() {
assert!((STATUS_EXL | STATUS_ERL | STATUS_KX).is_kernel_mode_address_segment()); assert!((Status::STATUS_EXL | Status::STATUS_ERL | Status::STATUS_KX).is_kernel_mode_address_segment());
} }
#[test] #[test]
......
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