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qSVS

Project information

SystemVerilog modeling of SFQ and AQFP gates, and the SFQ/AQFP interface circuits. The models are compatible with SDF (standard delay format) and friendly with the existing tools, they offer an easy debugging platform, modular and qualified for generalization and reproduction, elegant and conceptual, can encompass many circuit parameters, environmental effects, and advanced SCEphenomena.

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BSD 2-Clause "Simplified" License

Created on

April 16, 2019

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