• ccavazzoni's avatar
    - adding memory alignment directives to have a performance improvement on... · 9b8fce95
    ccavazzoni authored
    - adding memory alignment directives to have a performance improvement on Intel architecure (CPU+Network),
      only meaningful for intel compiler, shold be of no arm for all the other
    - Intel DFTI MKL fft interface back in again (with __DFTI) in fft_scalar, some issues with the fftw3 interface
      is prevending porting to Xeon PHI processor (no arm to all other procs/fft)
    - A split in thress different subs of the general driver (tg_cft3s) is added to the fft_parallel module,
      to support software pipelining optimizations, to mask communication and data transfer latency.
    
    
    git-svn-id: http://qeforge.qe-forge.org/svn/q-e/trunk/espresso@11407 c92efa57-630b-4861-b058-cf58834340f0
    9b8fce95
wavefunctions.f90 2.04 KB