Adds in FIFO Purge Before Record
Created by: ryan-summers
This pull request updates the FPGA bitstream to include a GPIO reset block. The firmware may now manually force the AXI STREAM FIFO feeding into the DMA engine into reset without resetting the rest of the system. This allows the data to be purged from the FIFO if it is stale. The firmware has been updated to properly purge FIFO contents before ping recordings begin. This addresses the issue brought up in https://github.com/PalouseRobosub/hydro-zynq/issues/3.