Commit 238e17cd authored by Mark J. Blair's avatar Mark J. Blair

Updated project status.

parent f86d352e
...@@ -44,12 +44,13 @@ to work on this project during October, 2016 for ...@@ -44,12 +44,13 @@ to work on this project during October, 2016 for
[Retrochallenge 2016/10](http://retrochallenge.org), but I do not [Retrochallenge 2016/10](http://retrochallenge.org), but I do not
realistically expect to complete this project within a month. realistically expect to complete this project within a month.
As of October 23: As of October 31:
* I have completed the first full routing of the main * I have completed the design of the main controller PCB.
controller PCB.
* Another PCB for bus termination is probably needed. * I have also completed the design of a small bus terminator PCB.
* I have created a preliminary design for a 3D printable case.
* FPGA design not yet started. * FPGA design not yet started.
......
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