Commit 9965b1ee authored by Mark J. Blair's avatar Mark J. Blair

Updated project status.

parent 8c74ea2a
......@@ -47,13 +47,18 @@ be quite satisfied if I manage to design and build the first version
of the controller board, leaving the much larger task of developing
the firmware and FPGA code for later.
As of October 16, I have completed a first draft of the schematic.
Most FPGA pin assignments are arbitrary, and will be changed during
PCB routing.
## Planned Features
* Single main controller board mounts on rear panel of RL02 drive in place
of original drive bus interface connectors. Uses original internal
drive bus ribbon cable.
* Requires +5VDC power, tapped from RL02 power supply.
* Requires 10-20 VDC power, tapped from RL02 power supply's +V UN REG
output, which is nominally around 16 VDC.
* USB 2.0 HS interface.
......@@ -77,6 +82,9 @@ the firmware and FPGA code for later.
* Main controller board connects to original RL02 logic card in place
of original drive bus, using 40 pin ribbon cable.
* Two headers provide 8 debugging outputs each from the FPGA and MCU,
for connection to a logic analyzer.
## References
Reference documents found at the following URLs are archived in the
......
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