Commit 5446cb75 authored by Mark J. Blair's avatar Mark J. Blair

Added FPGA project skeleton.

parent e9225f7d
*#
*~
*.ace
*.bak
*.cmd
*.cmd_log
*.cr.mti
*.elf
*.exe
*.ini
*.log
*.lso
*.ncd
*.scr
*.stx
*.svf
*.swp
*.vhi
*.wdb
*.xmsgs
*.xreport
*_beh.prj
db
impact.xsl
impact_impact.xwbt
incremental_db
pepExtractor.prj
planAhead_*
transcript
vsim.wlf
webtalk.log
webtalk_impact.xml
work
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Release 14.7 - Bitgen P.20131013 (lin64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
Loading device for application Rf_Device from file '6slx9.nph' in environment
/opt/Xilinx/14.7/ISE_DS/ISE/.
"RL02_USB" is an NCD, version 3.2, device xc6slx9, package tqg144, speed -2
Opened constraints file RL02_USB.pcf.
Sun Dec 25 11:32:27 2016
/opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/unwrapped/bitgen -filter iseconfig/filter.filter -intstyle ise -w -g DebugBitstream:No -g Binary:no -g CRC:Enable -g Reset_on_err:No -g ConfigRate:2 -g ProgPin:PullUp -g TckPin:PullUp -g TdiPin:PullUp -g TdoPin:PullUp -g TmsPin:PullUp -g UnusedPin:PullDown -g UserID:0xFFFFFFFF -g ExtMasterCclk_en:No -g SPI_buswidth:1 -g TIMER_CFG:0xFFFF -g multipin_wakeup:No -g StartUpClk:CClk -g DONE_cycle:4 -g GTS_cycle:5 -g GWE_cycle:6 -g LCK_cycle:NoWait -g Security:None -g DonePipe:Yes -g DriveDone:No -g en_sw_gsr:No -g drive_awake:No -g sw_clk:Startupclk -g sw_gwe_cycle:5 -g sw_gts_cycle:4 RL02_USB.ncd
Summary of Bitgen Options:
+----------------------+----------------------+
| Option Name | Current Setting |
+----------------------+----------------------+
| Compress | (Not Specified)* |
+----------------------+----------------------+
| Readback | (Not Specified)* |
+----------------------+----------------------+
| CRC | Enable** |
+----------------------+----------------------+
| DebugBitstream | No** |
+----------------------+----------------------+
| ConfigRate | 2** |
+----------------------+----------------------+
| StartupClk | Cclk** |
+----------------------+----------------------+
| DonePin | Pullup* |
+----------------------+----------------------+
| ProgPin | Pullup** |
+----------------------+----------------------+
| TckPin | Pullup** |
+----------------------+----------------------+
| TdiPin | Pullup** |
+----------------------+----------------------+
| TdoPin | Pullup** |
+----------------------+----------------------+
| TmsPin | Pullup** |
+----------------------+----------------------+
| UnusedPin | Pulldown** |
+----------------------+----------------------+
| GWE_cycle | 6** |
+----------------------+----------------------+
| GTS_cycle | 5** |
+----------------------+----------------------+
| LCK_cycle | NoWait** |
+----------------------+----------------------+
| DONE_cycle | 4** |
+----------------------+----------------------+
| Persist | No* |
+----------------------+----------------------+
| DriveDone | No** |
+----------------------+----------------------+
| DonePipe | Yes |
+----------------------+----------------------+
| Security | None** |
+----------------------+----------------------+
| UserID | 0xFFFFFFFF** |
+----------------------+----------------------+
| ActiveReconfig | No* |
+----------------------+----------------------+
| Partial | (Not Specified)* |
+----------------------+----------------------+
| Encrypt | No* |
+----------------------+----------------------+
| Key0 | pick* |
+----------------------+----------------------+
| StartCBC | pick* |
+----------------------+----------------------+
| KeyFile | (Not Specified)* |
+----------------------+----------------------+
| drive_awake | No** |
+----------------------+----------------------+
| Reset_on_err | No** |
+----------------------+----------------------+
| suspend_filter | Yes* |
+----------------------+----------------------+
| en_sw_gsr | No** |
+----------------------+----------------------+
| en_suspend | No* |
+----------------------+----------------------+
| sw_clk | Startupclk** |
+----------------------+----------------------+
| sw_gwe_cycle | 5** |
+----------------------+----------------------+
| sw_gts_cycle | 4** |
+----------------------+----------------------+
| multipin_wakeup | No** |
+----------------------+----------------------+
| wakeup_mask | 0x00* |
+----------------------+----------------------+
| ExtMasterCclk_en | No** |
+----------------------+----------------------+
| ExtMasterCclk_divide | 1* |
+----------------------+----------------------+
| CrcCoverage | No* |
+----------------------+----------------------+
| glutmask | Yes* |
+----------------------+----------------------+
| next_config_addr | 0x00000000* |
+----------------------+----------------------+
| next_config_new_mode | No* |
+----------------------+----------------------+
| next_config_boot_mode | 001* |
+----------------------+----------------------+
| next_config_register_write | Enable* |
+----------------------+----------------------+
| next_config_reboot | Enable* |
+----------------------+----------------------+
| golden_config_addr | 0x00000000* |
+----------------------+----------------------+
| failsafe_user | 0x0000* |
+----------------------+----------------------+
| TIMER_CFG | 0xFFFF |
+----------------------+----------------------+
| spi_buswidth | 1** |
+----------------------+----------------------+
| TimeStamp | Default* |
+----------------------+----------------------+
| IEEE1532 | No* |
+----------------------+----------------------+
| Binary | No** |
+----------------------+----------------------+
* Default setting.
** The specified setting matches the default setting.
There were 0 CONFIG constraint(s) processed from RL02_USB.pcf.
Running DRC.
DRC detected 0 errors and 0 warnings.
Creating bit map...
Saving bit stream in "RL02_USB.bit".
Bitstream generation is complete.
Release 14.7 ngdbuild P.20131013 (lin64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
Command Line: /opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/unwrapped/ngdbuild -filter
iseconfig/filter.filter -intstyle ise -dd _ngo -nt timestamp -uc RL02_USB.ucf -p
xc6slx9-tqg144-2 RL02_USB.ngc RL02_USB.ngd
Reading NGO file "/home/mblair/RL02-USB/fpga/RL02-USB/RL02_USB.ngc" ...
Gathering constraint information from source properties...
Done.
Annotating constraints to design from ucf file "RL02_USB.ucf" ...
Resolving constraint associations...
Checking Constraint Associations...
Done...
Checking expanded design ...
WARNING:NgdBuild:470 - bidirect pad net 'D<7>' has no legal driver
WARNING:NgdBuild:470 - bidirect pad net 'D<6>' has no legal driver
WARNING:NgdBuild:470 - bidirect pad net 'D<5>' has no legal driver
WARNING:NgdBuild:470 - bidirect pad net 'D<4>' has no legal driver
WARNING:NgdBuild:470 - bidirect pad net 'D<3>' has no legal driver
WARNING:NgdBuild:470 - bidirect pad net 'D<2>' has no legal driver
WARNING:NgdBuild:470 - bidirect pad net 'D<1>' has no legal driver
WARNING:NgdBuild:470 - bidirect pad net 'D<0>' has no legal driver
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
NGDBUILD Design Results Summary:
Number of errors: 0
Number of warnings: 8
Total memory usage is 402840 kilobytes
Writing NGD file "RL02_USB.ngd" ...
Total REAL time to NGDBUILD completion: 2 sec
Total CPU time to NGDBUILD completion: 2 sec
Writing NGDBUILD log file "RL02_USB.bld"...
Release 14.7 Drc P.20131013 (lin64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
Sun Dec 25 11:32:27 2016
drc -z RL02_USB.ncd RL02_USB.pcf
DRC detected 0 errors and 0 warnings.
XILINX-XDB 0.1 STUB 0.1 ASCII
XILINX-XDM V1.6e
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XILINX-XDB 0.1 STUB 0.1 ASCII
XILINX-XDM V1.6e
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\ No newline at end of file
Release 14.7 - par P.20131013 (lin64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
Sun Dec 25 11:32:18 2016
# NOTE: This file is designed to be imported into a spreadsheet program
# such as Microsoft Excel for viewing, printing and sorting. The |
# character is used as the data field separator. This file is also designed
# to support parsing.
#
INPUT FILE: RL02_USB_map.ncd
OUTPUT FILE: RL02_USB.pad
PART TYPE: xc6slx9
SPEED GRADE: -2
PACKAGE: tqg144
Pinout by Pin Number:
-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|
Pin Number|Signal Name|Pin Usage|Pin Name|Direction|IO Standard|IO Bank Number|Drive (mA)|Slew Rate|Termination|IOB Delay|Voltage|Constraint|IO Register|Signal Integrity|
P1||IOBS|IO_L83N_VREF_3|UNUSED||3|||||||||
P2||IOBM|IO_L83P_3|UNUSED||3|||||||||
P3|||GND||||||||||||
P4|||VCCO_3|||3|||||any******||||
P5||IOBS|IO_L52N_3|UNUSED||3|||||||||
P6||IOBM|IO_L52P_3|UNUSED||3|||||||||
P7||IOBS|IO_L51N_3|UNUSED||3|||||||||
P8||IOBM|IO_L51P_3|UNUSED||3|||||||||
P9||IOBS|IO_L50N_3|UNUSED||3|||||||||
P10||IOBM|IO_L50P_3|UNUSED||3|||||||||
P11||IOBS|IO_L49N_3|UNUSED||3|||||||||
P12||IOBM|IO_L49P_3|UNUSED||3|||||||||
P13|||GND||||||||||||
P14||IOBS|IO_L44N_GCLK20_3|UNUSED||3|||||||||
P15||IOBM|IO_L44P_GCLK21_3|UNUSED||3|||||||||
P16||IOBS|IO_L43N_GCLK22_IRDY2_3|UNUSED||3|||||||||
P17||IOBM|IO_L43P_GCLK23_3|UNUSED||3|||||||||
P18|||VCCO_3|||3|||||any******||||
P19|||VCCINT||||||||1.2||||
P20|||VCCAUX||||||||2.5||||
P21||IOBS|IO_L42N_GCLK24_3|UNUSED||3|||||||||
P22||IOBM|IO_L42P_GCLK25_TRDY2_3|UNUSED||3|||||||||
P23||IOBS|IO_L41N_GCLK26_3|UNUSED||3|||||||||
P24||IOBM|IO_L41P_GCLK27_3|UNUSED||3|||||||||
P25|||GND||||||||||||
P26||IOBS|IO_L37N_3|UNUSED||3|||||||||
P27||IOBM|IO_L37P_3|UNUSED||3|||||||||
P28|||VCCINT||||||||1.2||||
P29||IOBS|IO_L36N_3|UNUSED||3|||||||||
P30||IOBM|IO_L36P_3|UNUSED||3|||||||||
P31|||VCCO_3|||3|||||any******||||
P32||IOBS|IO_L2N_3|UNUSED||3|||||||||
P33||IOBM|IO_L2P_3|UNUSED||3|||||||||
P34||IOBS|IO_L1N_VREF_3|UNUSED||3|||||||||
P35||IOBM|IO_L1P_3|UNUSED||3|||||||||
P36|||VCCAUX||||||||2.5||||
P37|||PROGRAM_B_2||||||||||||
P38||IOBS|IO_L65N_CSO_B_2|UNUSED||2|||||||||
P39||IOBM|IO_L65P_INIT_B_2|UNUSED||2|||||||||
P40||IOBS|IO_L64N_D9_2|UNUSED||2|||||||||
P41|ACLO|IOB|IO_L64P_D8_2|OUTPUT|LVCMOS33|2|12|SLOW||||LOCATED|NO|NONE|
P42|||VCCO_2|||2|||||3.30||||
P43|DS<0>|IOB|IO_L62N_D6_2|OUTPUT|LVCMOS33|2|12|SLOW||||LOCATED|NO|NONE|
P44|DS<1>|IOB|IO_L62P_D5_2|OUTPUT|LVCMOS33|2|12|SLOW||||LOCATED|NO|NONE|
P45|WDATA|IOB|IO_L49N_D4_2|OUTPUT|LVCMOS33|2|12|SLOW||||LOCATED|NO|NONE|
P46|DRVCMD|IOB|IO_L49P_D3_2|OUTPUT|LVCMOS33|2|12|SLOW||||LOCATED|NO|NONE|
P47|STATCLK|IOB|IO_L48N_RDWR_B_VREF_2|INPUT|LVCMOS33|2||||NONE||LOCATED|NO|NONE|
P48|SECPLS|IOB|IO_L48P_D7_2|INPUT|LVCMOS33|2||||NONE||LOCATED|NO|NONE|
P49|||GND||||||||||||
P50|WG|IOB|IO_L31N_GCLK30_D15_2|OUTPUT|LVCMOS33|2|12|SLOW||||LOCATED|NO|NONE|
P51|SYSCLK|IOB|IO_L31P_GCLK31_D14_2|OUTPUT|LVCMOS33|2|12|SLOW||||LOCATED|NO|NONE|
P52|||VCCINT||||||||1.2||||
P53|||VCCAUX||||||||2.5||||
P54|||GND||||||||||||
P55|RDATA|IOB|IO_L30N_GCLK0_USERCCLK_2|INPUT|LVCMOS33|2||||NONE||LOCATED|NO|NONE|
P56|STATIN|IOB|IO_L30P_GCLK1_D13_2|INPUT|LVCMOS33|2||||NONE||LOCATED|NO|NONE|
P57|DRVRDY|IOB|IO_L14N_D12_2|INPUT|LVCMOS33|2||||NONE||LOCATED|NO|NONE|
P58|DRVERR|IOB|IO_L14P_D11_2|INPUT|LVCMOS33|2||||NONE||LOCATED|NO|NONE|
P59||IOBS|IO_L13N_D10_2|UNUSED||2|||||||||
P60||IOBM|IO_L13P_M1_2|UNUSED||2|||||||||
P61||IOBS|IO_L12N_D2_MISO3_2|UNUSED||2|||||||||
P62||IOBM|IO_L12P_D1_MISO2_2|UNUSED||2|||||||||
P63|||VCCO_2|||2|||||3.30||||
P64||IOBS|IO_L3N_MOSI_CSI_B_MISO0_2|UNUSED||2|||||||||
P65||IOBM|IO_L3P_D0_DIN_MISO_MISO1_2|UNUSED||2|||||||||
P66||IOBS|IO_L2N_CMPMOSI_2|UNUSED||2|||||||||
P67||IOBM|IO_L2P_CMPCLK_2|UNUSED||2|||||||||
P68|||GND||||||||||||
P69||IOBS|IO_L1N_M0_CMPMISO_2|UNUSED||2|||||||||
P70||IOBM|IO_L1P_CCLK_2|UNUSED||2|||||||||
P71|||DONE_2||||||||||||
P72|||CMPCS_B_2||||||||||||
P73|||SUSPEND||||||||||||
P74|WEn|IOB|IO_L74N_DOUT_BUSY_1|INPUT|LVCMOS33|1|||PULLUP|NONE||LOCATED|NO|NONE|
P75|OEn|IOB|IO_L74P_AWAKE_1|INPUT|LVCMOS33|1|||PULLUP|NONE||LOCATED|NO|NONE|
P76|||VCCO_1|||1|||||any******||||
P77|||GND||||||||||||
P78|D<3>|IOB|IO_L47N_1|INPUT|LVCMOS33|1||||NONE||LOCATED|NO|NONE|
P79|D<2>|IOB|IO_L47P_1|INPUT|LVCMOS33|1||||NONE||LOCATED|NO|NONE|
P80|CS1n|IOB|IO_L46N_1|INPUT|LVCMOS33|1|||PULLUP|NONE||LOCATED|NO|NONE|
P81|CS2n|IOB|IO_L46P_1|INPUT|LVCMOS33|1|||PULLUP|NONE||LOCATED|NO|NONE|
P82|A<0>|IOB|IO_L45N_1|INPUT|LVCMOS33|1||||NONE||LOCATED|NO|NONE|
P83|A<1>|IOB|IO_L45P_1|INPUT|LVCMOS33|1||||NONE||LOCATED|NO|NONE|
P84|A<2>|IOB|IO_L43N_GCLK4_1|INPUT|LVCMOS33|1||||NONE||LOCATED|NO|NONE|
P85|A<3>|IOB|IO_L43P_GCLK5_1|INPUT|LVCMOS33|1||||NONE||LOCATED|NO|NONE|
P86|||VCCO_1|||1|||||any******||||
P87|REFCLK|IOB|IO_L42N_GCLK6_TRDY1_1|INPUT|LVCMOS33|1||||NONE||LOCATED|NO|NONE|
P88|A<4>|IOB|IO_L42P_GCLK7_1|INPUT|LVCMOS33|1||||NONE||LOCATED|NO|NONE|
P89|||VCCINT||||||||1.2||||
P90|||VCCAUX||||||||2.5||||
P91|||GND||||||||||||
P92|A<5>|IOB|IO_L41N_GCLK8_1|INPUT|LVCMOS33|1||||NONE||LOCATED|NO|NONE|
P93|A<15>|IOB|IO_L41P_GCLK9_IRDY1_1|INPUT|LVCMOS33|1||||NONE||LOCATED|NO|NONE|
P94|A<14>|IOB|IO_L40N_GCLK10_1|INPUT|LVCMOS33|1||||NONE||LOCATED|NO|NONE|
P95|A<13>|IOB|IO_L40P_GCLK11_1|INPUT|LVCMOS33|1||||NONE||LOCATED|NO|NONE|
P96|||GND||||||||||||
P97|A<12>|IOB|IO_L34N_1|INPUT|LVCMOS33|1||||NONE||LOCATED|NO|NONE|
P98|D<1>|IOB|IO_L34P_1|INPUT|LVCMOS33|1||||NONE||LOCATED|NO|NONE|
P99|D<0>|IOB|IO_L33N_1|INPUT|LVCMOS33|1||||NONE||LOCATED|NO|NONE|
P100|A<6>|IOB|IO_L33P_1|INPUT|LVCMOS33|1||||NONE||LOCATED|NO|NONE|
P101|A<7>|IOB|IO_L32N_1|INPUT|LVCMOS33|1||||NONE||LOCATED|NO|NONE|
P102|A<8>|IOB|IO_L32P_1|INPUT|LVCMOS33|1||||NONE||LOCATED|NO|NONE|
P103|||VCCO_1|||1|||||any******||||
P104|A<9>|IOB|IO_L1N_VREF_1|INPUT|LVCMOS33|1||||NONE||LOCATED|NO|NONE|
P105|A<10>|IOB|IO_L1P_1|INPUT|LVCMOS33|1||||NONE||LOCATED|NO|NONE|
P106|||TDO||||||||||||
P107|||TMS||||||||||||
P108|||GND||||||||||||
P109|||TCK||||||||||||
P110|||TDI||||||||||||
P111|A<11>|IOB|IO_L66N_SCP0_0|INPUT|LVCMOS33|0||||NONE||LOCATED|NO|NONE|
P112|D<4>|IOB|IO_L66P_SCP1_0|INPUT|LVCMOS33|0||||NONE||LOCATED|NO|NONE|
P113|||GND||||||||||||
P114|D<5>|IOB|IO_L65N_SCP2_0|INPUT|LVCMOS33|0||||NONE||LOCATED|NO|NONE|
P115|D<6>|IOB|IO_L65P_SCP3_0|INPUT|LVCMOS33|0||||NONE||LOCATED|NO|NONE|
P116|D<7>|IOB|IO_L64N_SCP4_0|INPUT|LVCMOS33|0||||NONE||LOCATED|NO|NONE|
P117|FINT|IOB|IO_L64P_SCP5_0|OUTPUT|LVCMOS33|0|12|SLOW||||LOCATED|NO|NONE|
P118|FRESETn|IOB|IO_L63N_SCP6_0|INPUT|LVCMOS33|0|||PULLDOWN|NONE||LOCATED|NO|NONE|
P119||IOBM|IO_L63P_SCP7_0|UNUSED||0|||||||||
P120||IOBS|IO_L62N_VREF_0|UNUSED||0|||||||||
P121||IOBM|IO_L62P_0|UNUSED||0|||||||||
P122|||VCCO_0|||0|||||3.30||||
P123||IOBS|IO_L37N_GCLK12_0|UNUSED||0|||||||||
P124||IOBM|IO_L37P_GCLK13_0|UNUSED||0|||||||||
P125|||VCCO_0|||0|||||3.30||||
P126||IOBS|IO_L36N_GCLK14_0|UNUSED||0|||||||||
P127||IOBM|IO_L36P_GCLK15_0|UNUSED||0|||||||||
P128|||VCCINT||||||||1.2||||
P129|||VCCAUX||||||||2.5||||
P130|||GND||||||||||||
P131||IOBS|IO_L35N_GCLK16_0|UNUSED||0|||||||||
P132||IOBM|IO_L35P_GCLK17_0|UNUSED||0|||||||||
P133||IOBS|IO_L34N_GCLK18_0|UNUSED||0|||||||||
P134|FDEBUG<0>|IOB|IO_L34P_GCLK19_0|OUTPUT|LVCMOS33|0|12|SLOW||||LOCATED|NO|NONE|
P135|||VCCO_0|||0|||||3.30||||
P136|||GND||||||||||||
P137|FDEBUG<1>|IOB|IO_L4N_0|OUTPUT|LVCMOS33|0|12|SLOW||||LOCATED|NO|NONE|
P138|FDEBUG<2>|IOB|IO_L4P_0|OUTPUT|LVCMOS33|0|12|SLOW||||LOCATED|NO|NONE|
P139|FDEBUG<3>|IOB|IO_L3N_0|OUTPUT|LVCMOS33|0|12|SLOW||||LOCATED|NO|NONE|
P140|FDEBUG<4>|IOB|IO_L3P_0|OUTPUT|LVCMOS33|0|12|SLOW||||LOCATED|NO|NONE|
P141|FDEBUG<5>|IOB|IO_L2N_0|OUTPUT|LVCMOS33|0|12|SLOW||||LOCATED|NO|NONE|
P142|FDEBUG<6>|IOB|IO_L2P_0|OUTPUT|LVCMOS33|0|12|SLOW||||LOCATED|NO|NONE|
P143|FDEBUG<7>|IOB|IO_L1N_VREF_0|OUTPUT|LVCMOS33|0|12|SLOW||||LOCATED|NO|NONE|
P144||IOBM|IO_L1P_HSWAPEN_0|UNUSED||0|||||||||
-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|
* Default value.
** This default Pullup/Pulldown value can be overridden in Bitgen.
****** Special VCCO requirements may apply. Please consult the device
family datasheet for specific guideline on VCCO requirements.
This diff is collapsed.
//! **************************************************************************
// Written by: Map P.20131013 on Sun Dec 25 11:32:12 2016
//! **************************************************************************
SCHEMATIC START;
COMP "ACLO" LOCATE = SITE "P41" LEVEL 1;
COMP "A<1>" LOCATE = SITE "P83" LEVEL 1;
COMP "A<2>" LOCATE = SITE "P84" LEVEL 1;
COMP "A<3>" LOCATE = SITE "P85" LEVEL 1;
COMP "A<4>" LOCATE = SITE "P88" LEVEL 1;
COMP "A<5>" LOCATE = SITE "P92" LEVEL 1;
COMP "DRVCMD" LOCATE = SITE "P46" LEVEL 1;
COMP "A<6>" LOCATE = SITE "P100" LEVEL 1;
COMP "A<7>" LOCATE = SITE "P101" LEVEL 1;
COMP "A<8>" LOCATE = SITE "P102" LEVEL 1;
COMP "RDATA" LOCATE = SITE "P55" LEVEL 1;
COMP "A<9>" LOCATE = SITE "P104" LEVEL 1;
COMP "FDEBUG<0>" LOCATE = SITE "P134" LEVEL 1;
COMP "FDEBUG<1>" LOCATE = SITE "P137" LEVEL 1;
COMP "DS<0>" LOCATE = SITE "P43" LEVEL 1;
COMP "STATIN" LOCATE = SITE "P56" LEVEL 1;
COMP "FDEBUG<2>" LOCATE = SITE "P138" LEVEL 1;
COMP "DS<1>" LOCATE = SITE "P44" LEVEL 1;
COMP "D<0>" LOCATE = SITE "P99" LEVEL 1;
COMP "FRESETn" LOCATE = SITE "P118" LEVEL 1;
COMP "FDEBUG<3>" LOCATE = SITE "P139" LEVEL 1;
COMP "D<1>" LOCATE = SITE "P98" LEVEL 1;
COMP "FDEBUG<4>" LOCATE = SITE "P140" LEVEL 1;
COMP "REFCLK" LOCATE = SITE "P87" LEVEL 1;
COMP "D<2>" LOCATE = SITE "P79" LEVEL 1;
COMP "FDEBUG<5>" LOCATE = SITE "P141" LEVEL 1;
COMP "D<3>" LOCATE = SITE "P78" LEVEL 1;
COMP "FDEBUG<6>" LOCATE = SITE "P142" LEVEL 1;
COMP "D<4>" LOCATE = SITE "P112" LEVEL 1;
COMP "FDEBUG<7>" LOCATE = SITE "P143" LEVEL 1;
COMP "D<5>" LOCATE = SITE "P114" LEVEL 1;
COMP "WG" LOCATE = SITE "P50" LEVEL 1;
COMP "D<6>" LOCATE = SITE "P115" LEVEL 1;
COMP "D<7>" LOCATE = SITE "P116" LEVEL 1;
COMP "DRVERR" LOCATE = SITE "P58" LEVEL 1;
COMP "A<10>" LOCATE = SITE "P105" LEVEL 1;
COMP "A<11>" LOCATE = SITE "P111" LEVEL 1;
COMP "OEn" LOCATE = SITE "P75" LEVEL 1;
COMP "A<12>" LOCATE = SITE "P97" LEVEL 1;
COMP "A<13>" LOCATE = SITE "P95" LEVEL 1;
COMP "A<14>" LOCATE = SITE "P94" LEVEL 1;
COMP "CS1n" LOCATE = SITE "P80" LEVEL 1;
COMP "A<15>" LOCATE = SITE "P93" LEVEL 1;
COMP "CS2n" LOCATE = SITE "P81" LEVEL 1;
COMP "FINT" LOCATE = SITE "P117" LEVEL 1;
COMP "DRVRDY" LOCATE = SITE "P57" LEVEL 1;
COMP "SYSCLK" LOCATE = SITE "P51" LEVEL 1;
COMP "WEn" LOCATE = SITE "P74" LEVEL 1;
COMP "SECPLS" LOCATE = SITE "P48" LEVEL 1;
COMP "WDATA" LOCATE = SITE "P45" LEVEL 1;
COMP "STATCLK" LOCATE = SITE "P47" LEVEL 1;
COMP "A<0>" LOCATE = SITE "P82" LEVEL 1;
TIMEGRP REFCLK = BEL "sysclk_div_0" BEL "sysclk_div_1" BEL "sysclk_div_2" BEL
"sysclk_div_3" BEL "REFCLK_BUFGP/BUFG";
TS_REFCLK = PERIOD TIMEGRP "REFCLK" 15.24 ns HIGH 50% INPUT_JITTER 0.001 ns;
SCHEMATIC END;
verilog work "RL02_USB.v"
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# PlanAhead Generated IO constraints
NET "A[15]" IOSTANDARD = LVCMOS33;
NET "A[14]" IOSTANDARD = LVCMOS33;
NET "A[13]" IOSTANDARD = LVCMOS33;
NET "A[12]" IOSTANDARD = LVCMOS33;
NET "A[11]" IOSTANDARD = LVCMOS33;
NET "A[10]" IOSTANDARD = LVCMOS33;
NET "A[9]" IOSTANDARD = LVCMOS33;
NET "A[8]" IOSTANDARD = LVCMOS33;
NET "A[7]" IOSTANDARD = LVCMOS33;
NET "A[6]" IOSTANDARD = LVCMOS33;
NET "A[5]" IOSTANDARD = LVCMOS33;
NET "A[4]" IOSTANDARD = LVCMOS33;
NET "A[3]" IOSTANDARD = LVCMOS33;
NET "A[2]" IOSTANDARD = LVCMOS33;
NET "A[1]" IOSTANDARD = LVCMOS33;
NET "A[0]" IOSTANDARD = LVCMOS33;
NET "D[7]" IOSTANDARD = LVCMOS33;
NET "D[6]" IOSTANDARD = LVCMOS33;
NET "D[5]" IOSTANDARD = LVCMOS33;
NET "D[4]" IOSTANDARD = LVCMOS33;
NET "D[3]" IOSTANDARD = LVCMOS33;
NET "D[2]" IOSTANDARD = LVCMOS33;
NET "D[1]" IOSTANDARD = LVCMOS33;
NET "D[0]" IOSTANDARD = LVCMOS33;
NET "FDEBUG[7]" IOSTANDARD = LVCMOS33;
NET "FDEBUG[6]" IOSTANDARD = LVCMOS33;
NET "FDEBUG[5]" IOSTANDARD = LVCMOS33;
NET "FDEBUG[4]" IOSTANDARD = LVCMOS33;
NET "FDEBUG[3]" IOSTANDARD = LVCMOS33;
NET "FDEBUG[2]" IOSTANDARD = LVCMOS33;
NET "FDEBUG[1]" IOSTANDARD = LVCMOS33;
NET "FDEBUG[0]" IOSTANDARD = LVCMOS33;
NET "DS[1]" IOSTANDARD = LVCMOS33;
NET "DS[0]" IOSTANDARD = LVCMOS33;
NET "WG" IOSTANDARD = LVCMOS33;
NET "WDATA" IOSTANDARD = LVCMOS33;
NET "SYSCLK" IOSTANDARD = LVCMOS33;
NET "FINT" IOSTANDARD = LVCMOS33;
NET "DRVCMD" IOSTANDARD = LVCMOS33;
NET "ACLO" IOSTANDARD = LVCMOS33;
NET "WEn" IOSTANDARD = LVCMOS33;
NET "STATIN" IOSTANDARD = LVCMOS33;
NET "STATCLK" IOSTANDARD = LVCMOS33;
NET "SECPLS" IOSTANDARD = LVCMOS33;
NET "REFCLK" IOSTANDARD = LVCMOS33;
NET "RDATA" IOSTANDARD = LVCMOS33;
NET "OEn" IOSTANDARD = LVCMOS33;
NET "FRESETn" IOSTANDARD = LVCMOS33;
NET "DRVRDY" IOSTANDARD = LVCMOS33;
NET "DRVERR" IOSTANDARD = LVCMOS33;
NET "CS2n" IOSTANDARD = LVCMOS33;
NET "CS1n" IOSTANDARD = LVCMOS33;
# PlanAhead Generated physical constraints
NET "REFCLK" LOC = P87;
NET "CS1n" LOC = P80;
NET "CS2n" LOC = P81;
NET "DRVERR" LOC = P58;
NET "DRVRDY" LOC = P57;
NET "FRESETn" LOC = P118;
NET "OEn" LOC = P75;
NET "RDATA" LOC = P55;
NET "SECPLS" LOC = P48;
NET "STATCLK" LOC = P47;
NET "STATIN" LOC = P56;
NET "WEn" LOC = P74;
NET "ACLO" LOC = P41;
NET "DRVCMD" LOC = P46;
NET "FINT" LOC = P117;
NET "SYSCLK" LOC = P51;
NET "WDATA" LOC = P45;
NET "WG" LOC = P50;
NET "DS[0]" LOC = P43;
NET "DS[1]" LOC = P44;
NET "A[0]" LOC = P82;
NET "A[1]" LOC = P83;
NET "A[2]" LOC = P84;
NET "A[3]" LOC = P85;
NET "A[4]" LOC = P88;
NET "A[5]" LOC = P92;
NET "A[6]" LOC = P100;
NET "A[7]" LOC = P101;
NET "A[8]" LOC = P102;
NET "A[9]" LOC = P104;
NET "A[10]" LOC = P105;
NET "A[11]" LOC = P111;
NET "A[12]" LOC = P97;
NET "A[13]" LOC = P95;
NET "A[15]" LOC = P93;
NET "A[14]" LOC = P94;
NET "D[0]" LOC = P99;
NET "D[1]" LOC = P98;
NET "D[2]" LOC = P79;
NET "D[3]" LOC = P78;
NET "D[4]" LOC = P112;
NET "D[5]" LOC = P114;
NET "D[6]" LOC = P115;
NET "D[7]" LOC = P116;
NET "FDEBUG[0]" LOC = P134;
NET "FDEBUG[1]" LOC = P137;
NET "FDEBUG[2]" LOC = P138;
NET "FDEBUG[3]" LOC = P139;
NET "FDEBUG[4]" LOC = P140;
NET "FDEBUG[5]" LOC = P141;
NET "FDEBUG[6]" LOC = P142;
NET "FDEBUG[7]" LOC = P143;
# PlanAhead Generated IO constraints
NET "FRESETn" PULLDOWN;
NET "OEn" PULLUP;
NET "WEn" PULLUP;
NET "CS1n" PULLUP;
NET "CS2n" PULLUP;
#Created by Constraints Editor (xc6slx9-tqg144-2) - 2016/12/25
NET "REFCLK" TNM_NET = REFCLK;
TIMESPEC TS_REFCLK = PERIOD "REFCLK" 15.24 ns HIGH 50% INPUT_JITTER 1 ps;
Release 14.7 - par P.20131013 (lin64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
Sun Dec 25 11:32:18 2016
All signals are completely routed.
WARNING:ParHelpers:361 - There are 35 loadless signals in this design. This design will cause Bitgen to issue DRC
warnings.
A<0>_IBUF
A<10>_IBUF
A<11>_IBUF
A<12>_IBUF
A<13>_IBUF
A<14>_IBUF
A<15>_IBUF
A<1>_IBUF
A<2>_IBUF
A<3>_IBUF
A<4>_IBUF
A<5>_IBUF
A<6>_IBUF
A<7>_IBUF
A<8>_IBUF
A<9>_IBUF
CS1n_IBUF
CS2n_IBUF
D<0>_IBUF
D<1>_IBUF