Commit 2310c7fb authored by Mark J. Blair's avatar Mark J. Blair

Changed several component selections after deciding to mount on outside of...

Changed several component selections after deciding to mount on outside of rear panel instead of internally.
parent 896fb9b9
...@@ -20,9 +20,9 @@ at the end of the chain. Each individual drive contains servo logic ...@@ -20,9 +20,9 @@ at the end of the chain. Each individual drive contains servo logic
and related low-level functions, while the common controller card and related low-level functions, while the common controller card
contains the logic necessary to read and write data sectors. contains the logic necessary to read and write data sectors.
This project is a new controller card which mounts inside a single This project is a new controller card which mounts on the rear panel
RL02 drive in place of its original drive interface bus connector, and of a single RL02 drive in place of its original drive interface bus
provides a USB mass storage interface to the drive. connectors, and provides a USB mass storage interface to the drive.
Now, why would anybody do something so silly? Well, my goal is to use Now, why would anybody do something so silly? Well, my goal is to use
this modified drive for two purposes: this modified drive for two purposes:
...@@ -49,10 +49,9 @@ the firmware and FPGA code for later. ...@@ -49,10 +49,9 @@ the firmware and FPGA code for later.
## Planned Features ## Planned Features
* Single main controller board mounts in rear of RL02 drive in place * Single main controller board mounts on rear panel of RL02 drive in place
of original drive bus interface connectors. USB jack and other of original drive bus interface connectors. Uses original internal
connectors poke out through the original drive bus interface drive bus ribbon cable.
connector openings.
* Requires +5VDC power, tapped from RL02 power supply. * Requires +5VDC power, tapped from RL02 power supply.
...@@ -61,19 +60,19 @@ the firmware and FPGA code for later. ...@@ -61,19 +60,19 @@ the firmware and FPGA code for later.
* Presents RL02 media as a USB mass storage device. Block size is 256 * Presents RL02 media as a USB mass storage device. Block size is 256
bytes. bytes.
* (optional, TBD) LCD character display provides status information. * LCD character display inconveniently mounted on rear of drive
provides status information.
* Disk controller functions to be implemented in Xilinx Spartan-6 FPGA. * Disk controller functions to be implemented in Xilinx Spartan-6 FPGA.
* USB interface functions to be implemented in STM32F4 series * USB interface functions to be implemented in STM32F4 series
microcontroller. microcontroller.
* 14 pin, 2mm pitch FPGA JTAG header accessible at back panel. Use Xilinx Platform * 14 pin, 2mm pitch FPGA JTAG header. Use Xilinx Platform Cable,
Cable, Digilent JTAG-HS3, etc. Digilent JTAG-HS3, etc.
* 10 pin, 0.05" pitch microcontroller debug interface header accessible * 20 pin, 0.1" pitch microcontroller debug interface header. Use
at back panel. Use ST-Link/v2 or equivalent, with suitable ST-Link/v2 or equivalent.
cable/adapter.
* Main controller board connects to original RL02 logic card in place * Main controller board connects to original RL02 logic card in place
of original drive bus, using 40 pin ribbon cable. of original drive bus, using 40 pin ribbon cable.
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