Commit 00a5706c authored by Mark J. Blair's avatar Mark J. Blair

Routing checkpoint.

parent 6f634199
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......@@ -67,7 +67,7 @@ Comment3 ""
Comment4 ""
$EndDescr
$Sheet
S 900 950 1000 1000
S 900 950 1000 1000
U 57FBC2B8
F0 "Power" 60
F1 "Power.sch" 60
......@@ -77,106 +77,106 @@ S 6300 4150 1000 3100
U 57FBC3DA
F0 "MCU" 60
F1 "MCU.sch" 60
F2 "A0" O R 7300 4200 60
F3 "A1" O R 7300 4300 60
F4 "A2" O R 7300 4400 60
F5 "A3" O R 7300 4500 60
F6 "A4" O R 7300 4600 60
F7 "A5" O R 7300 4700 60
F8 "A6" O R 7300 4800 60
F9 "A7" O R 7300 4900 60
F10 "A8" O R 7300 5000 60
F11 "A9" O R 7300 5100 60
F12 "A10" O R 7300 5200 60
F13 "A11" O R 7300 5300 60
F14 "A12" O R 7300 5400 60
F15 "A13" O R 7300 5500 60
F16 "A14" O R 7300 5600 60
F17 "A15" O R 7300 5700 60
F18 "D0" B R 7300 5800 60
F19 "D1" B R 7300 5900 60
F20 "D2" B R 7300 6000 60
F21 "D3" B R 7300 6100 60
F22 "D4" B R 7300 6200 60
F23 "D5" B R 7300 6300 60
F24 "D6" B R 7300 6400 60
F25 "D7" B R 7300 6500 60
F26 "~CS1" O R 7300 6600 60
F27 "~CS2" O R 7300 6700 60
F28 "~OE" O R 7300 6800 60
F29 "~WE" O R 7300 6900 60
F30 "REFCLK" O R 7300 7000 60
F31 "~FRESET" O R 7300 7100 60
F32 "FINT" I R 7300 7200 60
F2 "A0" O R 7300 4200 60
F3 "A1" O R 7300 4300 60
F4 "A2" O R 7300 4400 60
F5 "A3" O R 7300 4500 60
F6 "A4" O R 7300 4600 60
F7 "A5" O R 7300 4700 60
F8 "A6" O R 7300 4800 60
F9 "A7" O R 7300 4900 60
F10 "A8" O R 7300 5000 60
F11 "A9" O R 7300 5100 60
F12 "A10" O R 7300 5200 60
F13 "A11" O R 7300 5300 60
F14 "A12" O R 7300 5400 60
F15 "A13" O R 7300 5500 60
F16 "A14" O R 7300 5600 60
F17 "A15" O R 7300 5700 60
F18 "D0" B R 7300 5800 60
F19 "D1" B R 7300 5900 60
F20 "D2" B R 7300 6000 60
F21 "D3" B R 7300 6100 60
F22 "D4" B R 7300 6200 60
F23 "D5" B R 7300 6300 60
F24 "D6" B R 7300 6400 60
F25 "D7" B R 7300 6500 60
F26 "~CS1" O R 7300 6600 60
F27 "~CS2" O R 7300 6700 60
F28 "~OE" O R 7300 6800 60
F29 "~WE" O R 7300 6900 60
F30 "REFCLK" O R 7300 7000 60
F31 "~FRESET" O R 7300 7100 60
F32 "FINT" I R 7300 7200 60
$EndSheet
$Sheet
S 7700 4150 1000 3100
U 57FBC4AC
F0 "FPGA" 60
F1 "FPGA.sch" 60
F2 "A0" I L 7700 4200 60
F3 "A1" I L 7700 4300 60
F4 "A2" I L 7700 4400 60
F5 "A3" I L 7700 4500 60
F6 "A4" I L 7700 4600 60
F7 "A5" I L 7700 4700 60
F8 "A6" I L 7700 4800 60
F9 "A7" I L 7700 4900 60
F10 "A8" I L 7700 5000 60
F11 "A9" I L 7700 5100 60
F12 "A10" I L 7700 5200 60
F13 "A11" I L 7700 5300 60
F14 "A13" I L 7700 5500 60
F15 "A12" I L 7700 5400 60
F16 "A14" I L 7700 5600 60
F17 "A15" I L 7700 5700 60
F18 "D0" I L 7700 5800 60
F19 "D1" I L 7700 5900 60
F20 "D2" I L 7700 6000 60
F21 "D3" I L 7700 6100 60
F22 "D4" I L 7700 6200 60
F23 "D5" I L 7700 6300 60
F24 "D6" I L 7700 6400 60
F25 "D7" I L 7700 6500 60
F26 "~CS1" I L 7700 6600 60
F27 "~CS2" I L 7700 6700 60
F28 "~OE" I L 7700 6800 60
F29 "~WE" I L 7700 6900 60
F30 "REFCLK" I L 7700 7000 60
F31 "ACLO" O R 8700 4200 60
F32 "DS0" O R 8700 4300 60
F33 "DS1" O R 8700 4400 60
F34 "WG" O R 8700 4500 60
F35 "SYSCLK" O R 8700 4600 60
F36 "WDATA" O R 8700 4700 60
F37 "DRVCMD" O R 8700 4800 60
F38 "RDATA" I R 8700 4900 60
F39 "STATIN" I R 8700 5000 60
F40 "STATCLK" I R 8700 5100 60
F41 "SECPLS" I R 8700 5200 60
F42 "DRVRDY" I R 8700 5300 60
F43 "DRVERR" I R 8700 5400 60
F44 "~FRESET" I L 7700 7100 60
F45 "FINT" O L 7700 7200 60
F2 "A0" I L 7700 4200 60
F3 "A1" I L 7700 4300 60
F4 "A2" I L 7700 4400 60
F5 "A3" I L 7700 4500 60
F6 "A4" I L 7700 4600 60
F7 "A5" I L 7700 4700 60
F8 "A6" I L 7700 4800 60
F9 "A7" I L 7700 4900 60
F10 "A8" I L 7700 5000 60
F11 "A9" I L 7700 5100 60
F12 "A10" I L 7700 5200 60
F13 "A11" I L 7700 5300 60
F14 "A13" I L 7700 5500 60
F15 "A12" I L 7700 5400 60
F16 "A14" I L 7700 5600 60
F17 "A15" I L 7700 5700 60
F18 "D0" I L 7700 5800 60
F19 "D1" I L 7700 5900 60
F20 "D2" I L 7700 6000 60
F21 "D3" I L 7700 6100 60
F22 "D4" I L 7700 6200 60
F23 "D5" I L 7700 6300 60
F24 "D6" I L 7700 6400 60
F25 "D7" I L 7700 6500 60
F26 "~CS1" I L 7700 6600 60
F27 "~CS2" I L 7700 6700 60
F28 "~OE" I L 7700 6800 60
F29 "~WE" I L 7700 6900 60
F30 "REFCLK" I L 7700 7000 60
F31 "ACLO" O R 8700 4200 60
F32 "DS0" O R 8700 4300 60
F33 "DS1" O R 8700 4400 60
F34 "WG" O R 8700 4500 60
F35 "SYSCLK" O R 8700 4600 60
F36 "WDATA" O R 8700 4700 60
F37 "DRVCMD" O R 8700 4800 60
F38 "RDATA" I R 8700 4900 60
F39 "STATIN" I R 8700 5000 60
F40 "STATCLK" I R 8700 5100 60
F41 "SECPLS" I R 8700 5200 60
F42 "DRVRDY" I R 8700 5300 60
F43 "DRVERR" I R 8700 5400 60
F44 "~FRESET" I L 7700 7100 60
F45 "FINT" O L 7700 7200 60
$EndSheet
$Sheet
S 9100 4150 1000 1300
U 57FBC501
F0 "DriveBus" 60
F1 "DriveBus.sch" 60
F2 "ACLO" I L 9100 4200 60
F3 "DS0" I L 9100 4300 60
F4 "DS1" I L 9100 4400 60
F5 "WG" I L 9100 4500 60
F6 "SYSCLK" I L 9100 4600 60
F7 "WDATA" I L 9100 4700 60
F8 "DRVCMD" I L 9100 4800 60
F9 "RDATA" O L 9100 4900 60
F10 "STATIN" O L 9100 5000 60
F11 "STATCLK" O L 9100 5100 60
F12 "SECPLS" O L 9100 5200 60
F13 "DRVRDY" O L 9100 5300 60
F14 "DRVERR" O L 9100 5400 60
F2 "ACLO" I L 9100 4200 60
F3 "DS0" I L 9100 4300 60
F4 "DS1" I L 9100 4400 60
F5 "WG" I L 9100 4500 60
F6 "SYSCLK" I L 9100 4600 60
F7 "WDATA" I L 9100 4700 60
F8 "DRVCMD" I L 9100 4800 60
F9 "RDATA" O L 9100 4900 60
F10 "STATIN" O L 9100 5000 60
F11 "STATCLK" O L 9100 5100 60
F12 "SECPLS" O L 9100 5200 60
F13 "DRVRDY" O L 9100 5300 60
F14 "DRVERR" O L 9100 5400 60
$EndSheet
Wire Wire Line
7300 4200 7700 4200
......
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