Commit a6c8b1d3 authored by Linaro CI's avatar Linaro CI

Merge remote-tracking branch 'bus-scaling/bus-scaling' into integration-linux-qcomlt

# Conflicts:
#	arch/arm64/boot/dts/qcom/msm8996.dtsi
#	arch/arm64/boot/dts/qcom/sdm845.dtsi
#	drivers/interconnect/core.c
#	drivers/interconnect/qcom/Kconfig
#	drivers/interconnect/qcom/Makefile
#	drivers/interconnect/qcom/sdm845.c
#	include/linux/interconnect-provider.h
#	include/linux/interconnect.h
parents e28681cf 5764a919
Qualcomm SMD-RPM interconnect driver binding
------------------------------------------------
The RPM (Resource Power Manager) is a dedicated hardware engine
for managing the shared SoC resources in order to keep the lowest
power profile. It communicates with other hardware subsystems via
the shared memory driver (SMD) back-end and accepts requests for
various resources.
Required properties :
- compatible : shall contain only one of the following:
"qcom,interconnect-smd-rpm"
Example:
smd {
compatible = "qcom,smd";
rpm {
interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
qcom,ipc = <&apcs 8 0>;
qcom,smd-edge = <15>;
rpm_requests {
compatible = "qcom,rpm-msm8916";
qcom,smd-channels = "rpm_requests";
interconnect-smd-rpm {
compatible = "qcom,interconnect-smd-rpm";
};
};
};
};
Qualcomm MSM8916 Network-On-Chip interconnect driver binding
----------------------------------------------------
Required properties :
- compatible : shall contain only one of the following:
"qcom,msm8916-bimc"
"qcom,msm8916-pnoc"
"qcom,msm8916-snoc"
- #interconnect-cells : should contain 1
- reg : shall contain base register location and length
Optional properties :
clocks : list of phandles and specifiers to all interconnect bus clocks
clock-names : clock names should include both "bus_clk" and "bus_a_clk"
Examples:
snoc: [email protected] {
compatible = "qcom,msm8916-snoc";
#interconnect-cells = <1>;
reg = <0x580000 0x14000>;
clock-names = "bus_clk", "bus_a_clk";
clocks = <&rpmcc RPM_SMD_SNOC_CLK>,
<&rpmcc RPM_SMD_SNOC_A_CLK>;
};
bimc: [email protected] {
compatible = "qcom,msm8916-bimc";
#interconnect-cells = <1>;
reg = <0x400000 0x62000>;
clock-names = "bus_clk", "bus_a_clk";
clocks = <&rpmcc RPM_SMD_BIMC_CLK>,
<&rpmcc RPM_SMD_BIMC_A_CLK>;
};
pnoc: [email protected] {
compatible = "qcom,msm8916-pnoc";
#interconnect-cells = <1>;
reg = <0x500000 0x11000>;
clock-names = "bus_clk", "bus_a_clk";
clocks = <&rpmcc RPM_SMD_PCNOC_CLK>,
<&rpmcc RPM_SMD_PCNOC_A_CLK>;
};
Qualcomm MSM8996 Network-On-Chip interconnect driver binding
----------------------------------------------------
Required properties :
- compatible : shall contain only one of the following:
"qcom,msm8996-a0noc"
"qcom,msm8996-a1noc"
"qcom,msm8996-a2noc"
"qcom,msm8996-bimc"
"qcom,msm8996-cnoc"
"qcom,msm8996-mmnoc"
"qcom,msm8996-snoc"
"qcom,msm8996-pnoc"
- #interconnect-cells : should contain 1
- reg : shall contain base register location and length
Optional properties :
clocks : list of phandles and specifiers to all interconnect bus clocks
clock-names : clock names should include both "bus_clk" and "bus_a_clk"
Examples:
bimc: [email protected] {
compatible = "qcom,msm8996-bimc";
#interconnect-cells = <1>;
reg = <0x400000 0x62000>;
clock-names = "bus_clk", "bus_a_clk";
clocks = <&rpmcc RPM_SMD_BIMC_CLK>,
<&rpmcc RPM_SMD_BIMC_A_CLK>;
};
cnoc: [email protected] {
compatible = "qcom,msm8996-cnoc";
#interconnect-cells = <1>;
reg = <0x500000 0x80>;
clock-names = "bus_clk", "bus_a_clk";
clocks = <&rpmcc RPM_SMD_CNOC_CLK>,
<&rpmcc RPM_SMD_CNOC_A_CLK>;
};
snoc: [email protected] {
compatible = "qcom,msm8996-snoc";
#interconnect-cells = <1>;
reg = <0x520000 0xa100>;
clock-names = "bus_clk", "bus_a_clk";
clocks = <&rpmcc RPM_SMD_SNOC_CLK>,
<&rpmcc RPM_SMD_SNOC_A_CLK>;
};
a0noc: [email protected] {
compatible = "qcom,msm8996-a0noc";
#interconnect-cells = <1>;
reg = <0x540000 0x5100>;
clock-names = "bus_clk", "bus_a_clk";
clocks = <&gcc GCC_AGGRE0_SNOC_AXI_CLK>,
<&gcc GCC_AGGRE0_SNOC_AXI_CLK>;
power-domains = <&gcc AGGRE0_NOC_GDSC>;
};
a1noc: [email protected] {
compatible = "qcom,msm8996-a1noc";
#interconnect-cells = <1>;
reg = <0x560000 0x3100>;
clock-names = "bus_clk", "bus_a_clk";
clocks = <&rpmcc RPM_SMD_AGGR1_NOC_CLK>,
<&rpmcc RPM_SMD_AGGR1_NOC_A_CLK>;
};
a2noc: [email protected] {
compatible = "qcom,msm8996-a2noc";
#interconnect-cells = <1>;
reg = <0x580000 0x8100>;
clock-names = "bus_clk", "bus_a_clk";
clocks = <&rpmcc RPM_SMD_AGGR2_NOC_CLK>,
<&rpmcc RPM_SMD_AGGR2_NOC_A_CLK>;
};
mmnoc: [email protected] {
compatible = "qcom,msm8996-mmnoc";
#interconnect-cells = <1>;
reg = <0x5a0000 0xb080>;
clock-names = "bus_clk", "bus_a_clk";
clocks = <&rpmcc RPM_SMD_MMAXI_CLK>,
<&rpmcc RPM_SMD_MMAXI_A_CLK>;
power-domains = <&mmcc MMAGIC_BIMC_GDSC>;
};
pnoc: [email protected] {
compatible = "qcom,msm8996-pnoc";
#interconnect-cells = <1>;
reg = <0x5c0000 0x2480>;
clock-names = "bus_clk", "bus_a_clk";
clocks = <&rpmcc RPM_SMD_PCNOC_CLK>,
<&rpmcc RPM_SMD_PCNOC_A_CLK>;
};
......@@ -11,6 +11,7 @@
* GNU General Public License for more details.
*/
#include <dt-bindings/interconnect/qcom,msm8916.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/qcom,gcc-msm8916.h>
#include <dt-bindings/reset/qcom,gcc-msm8916.h>
......@@ -1525,6 +1526,42 @@
#size-cells = <0>;
};
};
bimc: [email protected] {
compatible = "qcom,msm8916-bimc";
#interconnect-cells = <1>;
reg = <0x400000 0x62000>;
clock-names = "bus_clk", "bus_a_clk";
clocks = <&rpmcc RPM_SMD_BIMC_CLK>,
<&rpmcc RPM_SMD_BIMC_A_CLK>;
base-offset = <0>;
qos-offset = <0>;
status = "okay";
};
pnoc: [email protected] {
compatible = "qcom,msm8916-pnoc";
#interconnect-cells = <1>;
reg = <0x500000 0x11000>;
clock-names = "bus_clk", "bus_a_clk";
clocks = <&rpmcc RPM_SMD_PCNOC_CLK>,
<&rpmcc RPM_SMD_PCNOC_A_CLK>;
base-offset = <0x7000>;
qos-offset = <0x1000>;
status = "okay";
};
snoc: [email protected] {
compatible = "qcom,msm8916-snoc";
#interconnect-cells = <1>;
reg = <0x580000 0x14000>;
clock-names = "bus_clk", "bus_a_clk";
clocks = <&rpmcc RPM_SMD_SNOC_CLK>,
<&rpmcc RPM_SMD_SNOC_A_CLK>;
base-offset = <0x7000>;
qos-offset = <0x1000>;
status = "okay";
};
};
smd {
......@@ -1544,6 +1581,10 @@
#clock-cells = <1>;
};
interconnect-smd-rpm {
compatible = "qcom,interconnect-smd-rpm";
};
smd_rpm_regulators: pm8916-regulators {
compatible = "qcom,rpm-pm8916-regulators";
......
......@@ -3,6 +3,7 @@
* Copyright (c) 2014-2015, 2018 The Linux Foundation. All rights reserved.
*/
#include <dt-bindings/interconnect/qcom,msm8996.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/qcom,gcc-msm8996.h>
#include <dt-bindings/clock/qcom,mmcc-msm8996.h>
......@@ -821,6 +822,10 @@
};
};
interconnect-smd-rpm {
compatible = "qcom,interconnect-smd-rpm";
};
pm8994-regulators {
compatible = "qcom,rpm-pm8994-regulators";
......@@ -1790,6 +1795,108 @@
};
};
bimc: [email protected] {
compatible = "qcom,msm8996-bimc";
#interconnect-cells = <1>;
reg = <0x400000 0x62000>;
type = <2>;
base-offset = <0x8000>;
qos-offset = <0x4000>;
clock-names = "bus_clk", "bus_a_clk";
clocks = <&rpmcc RPM_SMD_BIMC_CLK>,
<&rpmcc RPM_SMD_BIMC_A_CLK>;
status = "okay";
};
cnoc: [email protected] {
compatible = "qcom,msm8996-cnoc";
#interconnect-cells = <1>;
reg = <0x500000 0x80>;
type = <1>;
clock-names = "bus_clk", "bus_a_clk";
clocks = <&rpmcc RPM_SMD_CNOC_CLK>,
<&rpmcc RPM_SMD_CNOC_A_CLK>;
status = "okay";
};
snoc: [email protected] {
compatible = "qcom,msm8996-snoc";
#interconnect-cells = <1>;
reg = <0x520000 0xa100>;
type = <1>;
base-offset = <0x4000>;
qos-offset = <0x1000>;
clock-names = "bus_clk", "bus_a_clk";
clocks = <&rpmcc RPM_SMD_SNOC_CLK>,
<&rpmcc RPM_SMD_SNOC_A_CLK>;
status = "okay";
};
a0noc: [email protected] {
compatible = "qcom,msm8996-a0noc";
#interconnect-cells = <1>;
reg = <0x540000 0x5100>;
type = <1>;
qcom,base-offset = <0x3000>;
qos-offset = <0x1000>;
clock-names = "bus_clk", "bus_a_clk";
clocks = <&gcc GCC_AGGRE0_SNOC_AXI_CLK>,
<&gcc GCC_AGGRE0_SNOC_AXI_CLK>;
power-domains = <&gcc AGGRE0_NOC_GDSC>;
status = "okay";
};
a1noc: [email protected] {
compatible = "qcom,msm8996-a1noc";
#interconnect-cells = <1>;
reg = <0x560000 0x3100>;
type = <1>;
base-offset = <0x2000>;
qos-offset = <0x1000>;
clock-names = "bus_clk", "bus_a_clk";
clocks = <&rpmcc RPM_SMD_AGGR1_NOC_CLK>,
<&rpmcc RPM_SMD_AGGR1_NOC_A_CLK>;
status = "okay";
};
a2noc: [email protected] {
compatible = "qcom,msm8996-a2noc";
#interconnect-cells = <1>;
reg = <0x580000 0x8100>;
base-offset = <0x3000>;
qos-offset = <0x1000>;
type = <1>;
clock-names = "bus_clk", "bus_a_clk";
clocks = <&rpmcc RPM_SMD_AGGR2_NOC_CLK>,
<&rpmcc RPM_SMD_AGGR2_NOC_A_CLK>;
status = "okay";
};
mmnoc: [email protected] {
compatible = "qcom,msm8996-mmnoc";
#interconnect-cells = <1>;
reg = <0x5a0000 0xb080>;
type = <1>;
base-offset = <0x4000>;
qos-offset = <0x1000>;
clock-names = "bus_clk", "bus_a_clk";
clocks = <&rpmcc RPM_SMD_MMAXI_CLK>,
<&rpmcc RPM_SMD_MMAXI_A_CLK>;
power-domains = <&mmcc MMAGIC_BIMC_GDSC>;
status = "okay";
};
pnoc: [email protected] {
compatible = "qcom,msm8996-pnoc";
#interconnect-cells = <1>;
reg = <0x5c0000 0x2480>;
type = <1>;
clock-names = "bus_clk", "bus_a_clk";
clocks = <&rpmcc RPM_SMD_PCNOC_CLK>,
<&rpmcc RPM_SMD_PCNOC_A_CLK>;
status = "okay";
};
slimbam:[email protected]
{
compatible = "qcom,bam-v1.7.0";
......@@ -2085,7 +2192,6 @@
};
sound: sound {
};
adsp-pil {
......
......@@ -11,6 +11,7 @@
#include <dt-bindings/clock/qcom,lpass-sdm845.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/clock/qcom,videocc-sdm845.h>
#include <dt-bindings/interconnect/qcom,sdm845.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/phy/phy-qcom-qusb2.h>
#include <dt-bindings/power/qcom-aoss-qmp.h>
......
......@@ -786,6 +786,11 @@ CONFIG_UNIPHIER_EFUSE=y
CONFIG_MESON_EFUSE=m
CONFIG_TEE=y
CONFIG_OPTEE=y
CONFIG_INTERCONNECT=y
CONFIG_INTERCONNECT_QCOM=y
CONFIG_INTERCONNECT_QCOM_MSM8916=y
CONFIG_INTERCONNECT_QCOM_MSM8996=y
CONFIG_INTERCONNECT_QCOM_SDM845=y
CONFIG_EXT2_FS=y
CONFIG_EXT3_FS=y
CONFIG_EXT4_FS_POSIX_ACL=y
......
......@@ -42,10 +42,12 @@ struct icc_req {
/**
* struct icc_path - interconnect path structure
* @tag: path tag
* @num_nodes: number of hops (nodes)
* @reqs: array of the requests applicable to this path of nodes
*/
struct icc_path {
u8 tag;
size_t num_nodes;
struct icc_req reqs[];
};
......@@ -206,7 +208,7 @@ static struct icc_path *path_find(struct device *dev, struct icc_node *src,
* implementing its own aggregate() function.
*/
static int aggregate_requests(struct icc_node *node)
static int aggregate_requests(struct icc_node *node, u8 tag)
{
struct icc_provider *p = node->provider;
struct icc_req *r;
......@@ -215,7 +217,7 @@ static int aggregate_requests(struct icc_node *node)
node->peak_bw = 0;
hlist_for_each_entry(r, &node->req_list, req_node)
p->aggregate(node, r->avg_bw, r->peak_bw,
p->aggregate(node, tag, r->avg_bw, r->peak_bw,
&node->avg_bw, &node->peak_bw);
return 0;
......@@ -396,6 +398,23 @@ struct icc_path *of_icc_get(struct device *dev, const char *name)
}
EXPORT_SYMBOL_GPL(of_icc_get);
/**
* icc_set_tag() - set tag on a path
* @path: the path we want to tag
* @tag: the tag value
*
* This function allows consumers to append a tag to the path, so that a
* different aggregation could be done based on this tag.
*/
void icc_set_tag(struct icc_path *path, u8 tag)
{
if (!path)
return;
path->tag = tag;
}
EXPORT_SYMBOL_GPL(icc_set_tag);
/**
* icc_set_bw() - set bandwidth constraints on an interconnect path
* @path: reference to the path returned by icc_get()
......@@ -434,7 +453,7 @@ int icc_set_bw(struct icc_path *path, u32 avg_bw, u32 peak_bw)
path->reqs[i].peak_bw = peak_bw;
/* aggregate requests for this node */
aggregate_requests(node);
aggregate_requests(node, path->tag);
}
ret = apply_constraints(path);
......@@ -446,7 +465,7 @@ int icc_set_bw(struct icc_path *path, u32 avg_bw, u32 peak_bw)
node = path->reqs[i].node;
path->reqs[i].avg_bw = old_avg;
path->reqs[i].peak_bw = old_peak;
aggregate_requests(node);
aggregate_requests(node, path->tag);
}
apply_constraints(path);
}
......
......@@ -11,3 +11,29 @@ config INTERCONNECT_QCOM_SDM845
help
This is a driver for the Qualcomm Network-on-Chip on sdm845-based
platforms.
config INTERCONNECT_QCOM_SMD_RPM
tristate "Qualcomm SMD RPM interconnect driver"
depends on INTERCONNECT_QCOM
depends on QCOM_SMD_RPM
help
This is a driver for communicating interconnect related configuration
details with a remote processor (RPM) on Qualcomm platforms.
config INTERCONNECT_QCOM_MSM8916
tristate "Qualcomm MSM8916 interconnect driver"
depends on INTERCONNECT_QCOM
depends on QCOM_SMD_RPM
select INTERCONNECT_QCOM_SMD_RPM
help
This is a driver for the Qualcomm Network-on-Chip on msm8916-based
platforms.
config INTERCONNECT_QCOM_MSM8996
tristate "Qualcomm MSM8996 interconnect driver"
depends on INTERCONNECT_QCOM
depends on QCOM_SMD_RPM
select INTERCONNECT_QCOM_SMD_RPM
help
This is a driver for the Qualcomm Network-on-Chip on msm8996-based
platforms.
# SPDX-License-Identifier: GPL-2.0
qnoc-sdm845-objs := sdm845.o
qnoc-smd-rpm-objs := smd-rpm.o
qnoc-msm8916-objs := msm8916.o
qnoc-msm8996-objs := msm8996.o
obj-$(CONFIG_INTERCONNECT_QCOM_SDM845) += qnoc-sdm845.o
obj-$(CONFIG_INTERCONNECT_QCOM_SMD_RPM) += qnoc-smd-rpm.o
obj-$(CONFIG_INTERCONNECT_QCOM_MSM8916) += qnoc-msm8916.o
obj-$(CONFIG_INTERCONNECT_QCOM_MSM8996) += qnoc-msm8996.o
This diff is collapsed.
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Qualcomm MSM8916 interconnect IDs
*
* Copyright (c) 2018, Linaro Ltd.
* Author: Georgi Djakov <[email protected]>
*/
#ifndef __DRIVERS_INTERCONNECT_QCOM_MSM8916_H
#define __DRIVERS_INTERCONNECT_QCOM_MSM8916_H
#define MSM8916_BIMC_SNOC_MAS 0
#define MSM8916_BIMC_SNOC_SLV 1
#define MSM8916_MASTER_AMPSS_M0 2
#define MSM8916_MASTER_LPASS 3
#define MSM8916_MASTER_BLSP_1 4
#define MSM8916_MASTER_DEHR 5
#define MSM8916_MASTER_GRAPHICS_3D 6
#define MSM8916_MASTER_JPEG 7
#define MSM8916_MASTER_MDP_PORT0 8
#define MSM8916_MASTER_CRYPTO_CORE0 9
#define MSM8916_MASTER_SDCC_1 10
#define MSM8916_MASTER_SDCC_2 11
#define MSM8916_MASTER_QDSS_BAM 12
#define MSM8916_MASTER_QDSS_ETR 13
#define MSM8916_MASTER_SNOC_CFG 14
#define MSM8916_MASTER_SPDM 15
#define MSM8916_MASTER_TCU0 16
#define MSM8916_MASTER_TCU1 17
#define MSM8916_MASTER_USB_HS 18
#define MSM8916_MASTER_VFE 19
#define MSM8916_MASTER_VIDEO_P0 20
#define MSM8916_SNOC_MM_INT_0 21
#define MSM8916_SNOC_MM_INT_1 22
#define MSM8916_SNOC_MM_INT_2 23
#define MSM8916_SNOC_MM_INT_BIMC 24
#define MSM8916_PNOC_INT_0 25
#define MSM8916_PNOC_INT_1 26
#define MSM8916_PNOC_MAS_0 27
#define MSM8916_PNOC_MAS_1 28
#define MSM8916_PNOC_SLV_0 29
#define MSM8916_PNOC_SLV_1 30
#define MSM8916_PNOC_SLV_2 31
#define MSM8916_PNOC_SLV_3 32
#define MSM8916_PNOC_SLV_4 33
#define MSM8916_PNOC_SLV_8 34
#define MSM8916_PNOC_SLV_9 35
#define MSM8916_PNOC_SNOC_MAS 36
#define MSM8916_PNOC_SNOC_SLV 37
#define MSM8916_SNOC_QDSS_INT 38
#define MSM8916_SLAVE_AMPSS_L2 39
#define MSM8916_SLAVE_APSS 40
#define MSM8916_SLAVE_LPASS 41
#define MSM8916_SLAVE_BIMC_CFG 42
#define MSM8916_SLAVE_BLSP_1 43
#define MSM8916_SLAVE_BOOT_ROM 44
#define MSM8916_SLAVE_CAMERA_CFG 45
#define MSM8916_SLAVE_CATS_128 46
#define MSM8916_SLAVE_OCMEM_64 47
#define MSM8916_SLAVE_CLK_CTL 48
#define MSM8916_SLAVE_CRYPTO_0_CFG 49
#define MSM8916_SLAVE_DEHR_CFG 50
#define MSM8916_SLAVE_DISPLAY_CFG 51
#define MSM8916_SLAVE_EBI_CH0 52
#define MSM8916_SLAVE_GRAPHICS_3D_CFG 53
#define MSM8916_SLAVE_IMEM_CFG 54
#define MSM8916_SLAVE_IMEM 55
#define MSM8916_SLAVE_MPM 56
#define MSM8916_SLAVE_MSG_RAM 57
#define MSM8916_SLAVE_MSS 58
#define MSM8916_SLAVE_PDM 59
#define MSM8916_SLAVE_PMIC_ARB 60
#define MSM8916_SLAVE_PNOC_CFG 61
#define MSM8916_SLAVE_PRNG 62
#define MSM8916_SLAVE_QDSS_CFG 63
#define MSM8916_SLAVE_QDSS_STM 64
#define MSM8916_SLAVE_RBCPR_CFG 65
#define MSM8916_SLAVE_SDCC_1 66
#define MSM8916_SLAVE_SDCC_2 67
#define MSM8916_SLAVE_SECURITY 68
#define MSM8916_SLAVE_SNOC_CFG 69
#define MSM8916_SLAVE_SPDM 70
#define MSM8916_SLAVE_SRVC_SNOC 71
#define MSM8916_SLAVE_TCSR 72
#define MSM8916_SLAVE_TLMM 73
#define MSM8916_SLAVE_USB_HS 74
#define MSM8916_SLAVE_VENUS_CFG 75
#define MSM8916_SNOC_BIMC_0_MAS 76
#define MSM8916_SNOC_BIMC_0_SLV 77
#define MSM8916_SNOC_BIMC_1_MAS 78
#define MSM8916_SNOC_BIMC_1_SLV 79
#define MSM8916_SNOC_INT_0 80
#define MSM8916_SNOC_INT_1 81
#define MSM8916_SNOC_INT_BIMC 82
#define MSM8916_SNOC_PNOC_MAS 83
#define MSM8916_SNOC_PNOC_SLV 84
#endif
This diff is collapsed.
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Qualcomm MSM8996 interconnect IDs
*
* Copyright (c) 2018, Linaro Ltd.
* Author: Georgi Djakov <[email protected]>
*/
#ifndef __DRIVERS_INTERCONNECT_QCOM_MSM8996_H
#define __DRIVERS_INTERCONNECT_QCOM_MSM8996_H
#define MSM8996_A0NOC_SNOC_MAS 0
#define MSM8996_A1NOC_SNOC_MAS 1
#define MSM8996_A2NOC_SNOC_MAS 2
#define MSM8996_MASTER_AMPSS_M0 3
#define MSM8996_BIMC_SNOC_MAS 4
#define MSM8996_BIMC_SNOC_1_MAS 5
#define MSM8996_MASTER_BLSP_1 6
#define MSM8996_MASTER_BLSP_2 7
#define MSM8996_CNOC_A1NOC_MAS 8
#define MSM8996_MASTER_CNOC_MNOC_CFG 9
#define MSM8996_MASTER_CNOC_MNOC_MMSS_CFG 10
#define MSM8996_MASTER_CPP 11
#define MSM8996_MASTER_CRYPTO_CORE0 12
#define MSM8996_MASTER_HMSS 13
#define MSM8996_MASTER_IPA 14
#define MSM8996_MASTER_JPEG 15
#define MSM8996_MASTER_MDP_PORT0 16
#define MSM8996_MASTER_MDP_PORT1 17
#define MSM8996_MNOC_BIMC_MAS 18
#define MSM8996_MASTER_GRAPHICS_3D 19
#define MSM8996_MASTER_PCIE 20
#define MSM8996_MASTER_PCIE_1 21
#define MSM8996_MASTER_PCIE_2 22
#define MSM8996_PNOC_A1NOC_MAS 23
#define MSM8996_MASTER_QDSS_BAM 24
#define MSM8996_MASTER_QDSS_DAP 25
#define MSM8996_MASTER_QDSS_ETR 26
#define MSM8996_MASTER_ROTATOR 27
#define MSM8996_MASTER_SDCC_1 28
#define MSM8996_MASTER_SDCC_2 29
#define MSM8996_MASTER_SDCC_4 30
#define MSM8996_SNOC_BIMC_MAS 31
#define MSM8996_MASTER_SNOC_CFG 32
#define MSM8996_SNOC_CNOC_MAS 33
#define MSM8996_SNOC_PNOC_MAS 34
#define MSM8996_MASTER_SNOC_VMEM 35
#define MSM8996_MASTER_TSIF 36
#define MSM8996_MASTER_UFS 37
#define MSM8996_MASTER_USB3 38
#define MSM8996_MASTER_USB_HS 39
#define MSM8996_MASTER_VIDEO_P0 40
#define MSM8996_MASTER_VIDEO_P0_OCMEM 41
#define MSM8996_MASTER_VFE 42
#define MSM8996_SLAVE_A0NOC_CFG 43
#define MSM8996_SLAVE_A0NOC_MPU_CFG 44
#define MSM8996_SLAVE_A0NOC_SMMU_CFG 45
#define MSM8996_A0NOC_SNOC_SLV 46
#define MSM8996_SLAVE_A1NOC_CFG 47
#define MSM8996_SLAVE_A1NOC_MPU_CFG 48
#define MSM8996_SLAVE_A1NOC_SMMU_CFG 49
#define MSM8996_A1NOC_SNOC_SLV 50
#define MSM8996_SLAVE_A2NOC_CFG 51
#define MSM8996_SLAVE_A2NOC_MPU_CFG 52
#define MSM8996_SLAVE_A2NOC_SMMU_CFG 53
#define MSM8996_A2NOC_SNOC_SLV 54
#define MSM8996_SLAVE_AHB2PHY 55
#define MSM8996_SLAVE_BIMC_CFG 56
#define MSM8996_BIMC_SNOC_SLV 57
#define MSM8996_BIMC_SNOC_1_SLV 58
#define MSM8996_SLAVE_BLSP_1 59
#define MSM8996_SLAVE_BLSP_2 60
#define MSM8996_SLAVE_CAMERA_CFG 61
#define MSM8996_SLAVE_CAMERA_THROTTLE_CFG 62
#define MSM8996_SLAVE_CLK_CTL 63
#define MSM8996_CNOC_SNOC_SLV 64
#define MSM8996_SLAVE_CNOC_MNOC_CFG 65
#define MSM8996_SLAVE_CNOC_MNOC_MMSS_CFG 66
#define MSM8996_SLAVE_QDSS_RBCPR_APU_CFG 67
#define MSM8996_SLAVE_CPR_CFG 68
#define MSM8996_SLAVE_CRYPTO_0_CFG 69
#define MSM8996_SLAVE_DCC_CFG 70
#define MSM8996_SLAVE_DISPLAY_CFG 71
#define MSM8996_SLAVE_DISPLAY_THROTTLE_CFG 72
#define MSM8996_SLAVE_DSA_CFG 73
#define MSM8996_SLAVE_DSA_MPU_CFG 74
#define MSM8996_SLAVE_EBI1_PHY_CFG 75
#define MSM8996_SLAVE_EBI_CH0 76
#define MSM8996_SLAVE_HMSS_L3 77
#define MSM8996_SLAVE_APPSS 78
#define MSM8996_SLAVE_IMEM_CFG 79
#define MSM8996_SLAVE_OCIMEM 80
#define MSM8996_SLAVE_LPASS 81
#define MSM8996_SLAVE_LPASS_SMMU_CFG 82
#define MSM8996_SLAVE_MESSAGE_RAM 83
#define MSM8996_SLAVE_MISC_CFG 84
#define MSM8996_SLAVE_MMAGIC_CFG 85
#define MSM8996_MNOC_BIMC_SLV 86
#define MSM8996_SLAVE_MMSS_CLK_CFG 87
#define MSM8996_SLAVE_MNOC_MPU_CFG 88
#define MSM8996_SLAVE_MPM 89
#define MSM8996_SLAVE_GRAPHICS_3D_CFG 90
#define MSM8996_SLAVE_PCIE_0_CFG 91
#define MSM8996_SLAVE_PCIE_0 92
#define MSM8996_SLAVE_PCIE_1_CFG 93
#define MSM8996_SLAVE_PCIE_1 94
#define MSM8996_SLAVE_PCIE20_AHB2PHY 95
#define MSM8996_SLAVE_PCIE_2_CFG 96
#define MSM8996_SLAVE_PCIE_2 97
#define MSM8996_SLAVE_PDM 98
#define MSM8996_SLAVE_PIMEM_CFG 99
#define MSM8996_SLAVE_PIMEM 100
#define MSM8996_SLAVE_PMIC_ARB 101
#define MSM8996_PNOC_A1NOC_SLV 102
#define MSM8996_SLAVE_PRNG 103
#define MSM8996_SLAVE_QDSS_CFG 104
#define MSM8996_SLAVE_QDSS_STM 105
#define MSM8996_SLAVE_RBCPR_CX 106
#define MSM8996_SLAVE_RBCPR_MX 107
#define MSM8996_SLAVE_SDCC_1 108
#define MSM8996_SLAVE_SDCC_2 109
#define MSM8996_SLAVE_SDCC_4 110
#define MSM8996_SLAVE_SMMU_CPP_CFG 111
#define MSM8996_SLAVE_SMMU_JPEG_CFG 112
#define MSM8996_SLAVE_SMMU_MDP_CFG 113
#define MSM8996_SLAVE_SMMU_ROTATOR_CFG 114
#define MSM8996_SLAVE_SMMU_VENUS_CFG 115
#define MSM8996_SLAVE_SMMU_VFE_CFG 116
#define MSM8996_SNOC_BIMC_SLV 117
#define MSM8996_SLAVE_SNOC_CFG 118
#define MSM8996_SNOC_CNOC_SLV 119
#define MSM8996_SLAVE_SNOC_MPU_CFG 120
#define MSM8996_SNOC_PNOC_SLV 121
#define MSM8996_SLAVE_SNOC_VMEM 122