Commit efe820ff authored by Paul Molloy's avatar Paul Molloy

Initial changes to migrate from bare betal cortex M0 to discovery 072

board.

Reserving space for all IRQ vectors and setting to default vector
Updating linker script to memory setup of stm32f0 chips
parent 496fcb49
......@@ -6,8 +6,6 @@ BUILD = build
#doesn't need to be associated with any file names
PROJ = baremetal
# Core frequency in Hz
F_CPU = 8000000
# Selecting Core
CORTEX_M=0
......@@ -36,7 +34,7 @@ ARCH_FLAGS=-mthumb -mcpu=cortex-m$(CORTEX_M)
STARTUP=$(BASE)/startup/startup_ARM$(CORE).S
# -Os -flto -ffunction-sections -fdata-sections to compile for code size
CFLAGS=$(ARCH_FLAGS) $(STARTUP_DEFS) -DF_CPU=$(F_CPU) -Os -flto -ffunction-sections -fdata-sections
CFLAGS=$(ARCH_FLAGS) $(STARTUP_DEFS) -Os -flto -ffunction-sections -fdata-sections
CXXFLAGS=$(CFLAGS)
# Link for code size
......@@ -50,6 +48,12 @@ STARTUP_DEFS=-D__STARTUP_CLEAR_BSS -D__START=main
LDSCRIPTS=-L. -L$(BASE)/ldscripts -T nokeep.ld
LFLAGS=$(USE_NANO) $(USE_NOHOST) $(LDSCRIPTS) $(GC) $(MAP)
DEFINE+=\
-DSTM32F072xB \
-DF_CPU=8000000
INCLUDE=-I ./include
CFLAGS+= $(DEFINE) $(INCLUDE)
SOURCES=$(wildcard source/**/*.c source/*.c)
OBJECTS=$(patsubst %.c,%.o,$(SOURCES))
......
No preview for this file type
No preview for this file type
No preview for this file type
:100000000020001045000000850000008500000071
:020000040800F2
:1000000000000110C1000008010100080101000802
:1000100000000000000000000000000000000000E0
:10002000000000000000000000000000850000004B
:1000300000000000000000008500000085000000B6
:10004000850000000A490B4A0B4B9B1A03DD043B59
:10005000C858D050FBDC0949094A0020521A02DD79
:10006000043A8850FCDC00F010F800F00DF80000B5
:1000700094000000000000100000001000000010BC
:1000800000000010FEE7C046FEE77047F8B5C04626
:04009000F8B5C046B9
:0400000300000045B4
:1000200000000000000000000000000001010008C6
:1000300000000000000000000101000801010008AC
:100040000101000801010008010100080101000888
:100050000101000801010008010100080101000878
:100060000101000801010008010100080101000868
:100070000101000801010008010100080101000858
:100080000101000801010008010100080101000848
:100090000101000801010008010100080101000838
:1000A0000101000801010008010100080101000828
:1000B0000101000801010008010100080101000818
:1000C0000A490B4A0B4B9B1A03DD043BC858D0501E
:1000D000FBDC0949094A0020521A02DD043A885023
:1000E000FCDC00F010F800F00DF800001001000832
:1000F00000000010000000100000001000000010C0
:10010000FEE7C046FEE77047F8B5C046F8B5C04602
:04000005080000C12E
:00000001FF
......@@ -40,12 +40,12 @@ Discarded input sections
.ARM.exidx 0x00000000 0x8 c:/program files (x86)/gnu tools arm embedded/6.2 2016q4/bin/../lib/gcc/arm-none-eabi/6.2.1/../../../../arm-none-eabi/lib/thumb/v6-m/crt0.o
.ARM.attributes
0x00000000 0x1b c:/program files (x86)/gnu tools arm embedded/6.2 2016q4/bin/../lib/gcc/arm-none-eabi/6.2.1/../../../../arm-none-eabi/lib/thumb/v6-m/crt0.o
.data 0x00000000 0x0 C:\Users\Paul\AppData\Local\Temp\ccQBXc5q.o
.bss 0x00000000 0x0 C:\Users\Paul\AppData\Local\Temp\ccQBXc5q.o
.data 0x00000000 0x0 C:\Users\Paul\AppData\Local\Temp\ccy2ub8W.o
.bss 0x00000000 0x0 C:\Users\Paul\AppData\Local\Temp\ccy2ub8W.o
.text 0x00000000 0x0 source/minimum.o (symbol from plugin)
.text 0x00000000 0x0 C:\Users\Paul\AppData\Local\Temp\cc6fO4mu.ltrans0.ltrans.o
.data 0x00000000 0x0 C:\Users\Paul\AppData\Local\Temp\cc6fO4mu.ltrans0.ltrans.o
.bss 0x00000000 0x0 C:\Users\Paul\AppData\Local\Temp\cc6fO4mu.ltrans0.ltrans.o
.text 0x00000000 0x0 C:\Users\Paul\AppData\Local\Temp\ccg6fkcI.ltrans0.ltrans.o
.data 0x00000000 0x0 C:\Users\Paul\AppData\Local\Temp\ccg6fkcI.ltrans0.ltrans.o
.bss 0x00000000 0x0 C:\Users\Paul\AppData\Local\Temp\ccg6fkcI.ltrans0.ltrans.o
.text 0x00000000 0x0 c:/program files (x86)/gnu tools arm embedded/6.2 2016q4/bin/../lib/gcc/arm-none-eabi/6.2.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc.a(lib_a-exit.o)
.data 0x00000000 0x0 c:/program files (x86)/gnu tools arm embedded/6.2 2016q4/bin/../lib/gcc/arm-none-eabi/6.2.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc.a(lib_a-exit.o)
.bss 0x00000000 0x0 c:/program files (x86)/gnu tools arm embedded/6.2 2016q4/bin/../lib/gcc/arm-none-eabi/6.2.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc.a(lib_a-exit.o)
......@@ -139,8 +139,8 @@ Discarded input sections
Memory Configuration
Name Origin Length Attributes
FLASH 0x00000000 0x00020000 xr
RAM 0x10000000 0x00002000 xrw
FLASH 0x08000000 0x00020000 xr
RAM 0x10000000 0x00010000 xrw
*default* 0x00000000 0xffffffff
Linker script and memory map
......@@ -148,9 +148,9 @@ Linker script and memory map
LOAD c:/program files (x86)/gnu tools arm embedded/6.2 2016q4/bin/../lib/gcc/arm-none-eabi/6.2.1/thumb/v6-m/crti.o
LOAD c:/program files (x86)/gnu tools arm embedded/6.2 2016q4/bin/../lib/gcc/arm-none-eabi/6.2.1/thumb/v6-m/crtbegin.o
LOAD c:/program files (x86)/gnu tools arm embedded/6.2 2016q4/bin/../lib/gcc/arm-none-eabi/6.2.1/../../../../arm-none-eabi/lib/thumb/v6-m/crt0.o
LOAD C:\Users\Paul\AppData\Local\Temp\ccQBXc5q.o
LOAD C:\Users\Paul\AppData\Local\Temp\ccy2ub8W.o
LOAD source/minimum.o
LOAD C:\Users\Paul\AppData\Local\Temp\cc6fO4mu.ltrans0.ltrans.o
LOAD C:\Users\Paul\AppData\Local\Temp\ccg6fkcI.ltrans0.ltrans.o
START GROUP
LOAD c:/program files (x86)/gnu tools arm embedded/6.2 2016q4/bin/../lib/gcc/arm-none-eabi/6.2.1/thumb/v6-m\libgcc.a
LOAD c:/program files (x86)/gnu tools arm embedded/6.2 2016q4/bin/../lib/gcc/arm-none-eabi/6.2.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc.a
......@@ -163,32 +163,64 @@ END GROUP
LOAD c:/program files (x86)/gnu tools arm embedded/6.2 2016q4/bin/../lib/gcc/arm-none-eabi/6.2.1/thumb/v6-m/crtend.o
LOAD c:/program files (x86)/gnu tools arm embedded/6.2 2016q4/bin/../lib/gcc/arm-none-eabi/6.2.1/thumb/v6-m/crtn.o
.text 0x00000000 0x94
.text 0x08000000 0x110
*(.isr_vector)
.isr_vector 0x00000000 0x44 C:\Users\Paul\AppData\Local\Temp\ccQBXc5q.o
0x00000000 __isr_vector
.isr_vector 0x08000000 0xc0 C:\Users\Paul\AppData\Local\Temp\ccy2ub8W.o
0x08000000 __isr_vector
*(.text*)
.text 0x00000044 0x44 C:\Users\Paul\AppData\Local\Temp\ccQBXc5q.o
0x00000044 Reset_Handler
0x00000084 PendSV_Handler
0x00000084 NMI_Handler
0x00000084 SysTick_Handler
0x00000084 Default_Handler
0x00000084 SVC_Handler
0x00000084 DEF_IRQHandler
0x00000084 HardFault_Handler
.text 0x080000c0 0x44 C:\Users\Paul\AppData\Local\Temp\ccy2ub8W.o
0x080000c0 Reset_Handler
0x08000100 TSC_IRQHandler
0x08000100 HardFault_Handler
0x08000100 ADC1_COMP_IRQHandler
0x08000100 SysTick_Handler
0x08000100 PendSV_Handler
0x08000100 NMI_Handler
0x08000100 I2C1_IRQHandler
0x08000100 RCC_CRS_IRQHandler
0x08000100 SPI1_IRQHandler
0x08000100 TIM6_DAC_IRQHandler
0x08000100 USART3_4_IRQHandler
0x08000100 EXTI2_3_IRQHandler
0x08000100 I2C2_IRQHandler
0x08000100 TIM17_IRQHandler
0x08000100 CEC_CAN_IRQHandler
0x08000100 PVD_VDDIO2_IRQHandler
0x08000100 TIM1_CC_IRQHandler
0x08000100 DMA1_Channel4_5_6_7_IRQHandler
0x08000100 TIM16_IRQHandler
0x08000100 TIM3_IRQHandler
0x08000100 EXTI4_15_IRQHandler
0x08000100 DMA1_Channel1_IRQHandler
0x08000100 Default_Handler
0x08000100 TIM14_IRQHandler
0x08000100 TIM7_IRQHandler
0x08000100 TIM15_IRQHandler
0x08000100 EXTI0_1_IRQHandler
0x08000100 USB_IRQHandler
0x08000100 SPI2_IRQHandler
0x08000100 SVC_Handler
0x08000100 RTC_IRQHand
0x08000100 WWDG_IRQHandler
0x08000100 TIM2_IRQHandler
0x08000100 DEF_IRQHandler
0x08000100 DMA1_Channel2_3_IRQHandler
0x08000100 USART2_IRQHandler
0x08000100 FLASH_IRQHandler
0x08000100 USART1_IRQHandler
0x08000100 TIM1_BRK_UP_TRG_COM_IRQHandler
.text.startup.main
0x00000088 0x2 C:\Users\Paul\AppData\Local\Temp\cc6fO4mu.ltrans0.ltrans.o
0x00000088 main
0x08000104 0x2 C:\Users\Paul\AppData\Local\Temp\ccg6fkcI.ltrans0.ltrans.o
0x08000104 main
.text.SystemInit
0x0000008a 0x2 C:\Users\Paul\AppData\Local\Temp\cc6fO4mu.ltrans0.ltrans.o
0x0000008a SystemInit
0x08000106 0x2 C:\Users\Paul\AppData\Local\Temp\ccg6fkcI.ltrans0.ltrans.o
0x08000106 SystemInit
*(.init)
.init 0x0000008c 0x4 c:/program files (x86)/gnu tools arm embedded/6.2 2016q4/bin/../lib/gcc/arm-none-eabi/6.2.1/thumb/v6-m/crti.o
0x0000008c _init
.init 0x08000108 0x4 c:/program files (x86)/gnu tools arm embedded/6.2 2016q4/bin/../lib/gcc/arm-none-eabi/6.2.1/thumb/v6-m/crti.o
0x08000108 _init
*(.fini)
.fini 0x00000090 0x4 c:/program files (x86)/gnu tools arm embedded/6.2 2016q4/bin/../lib/gcc/arm-none-eabi/6.2.1/thumb/v6-m/crti.o
0x00000090 _fini
.fini 0x0800010c 0x4 c:/program files (x86)/gnu tools arm embedded/6.2 2016q4/bin/../lib/gcc/arm-none-eabi/6.2.1/thumb/v6-m/crti.o
0x0800010c _fini
*crtbegin.o(.ctors)
*crtbegin?.o(.ctors)
*(EXCLUDE_FILE(*crtend.o *crtend?.o) .ctors)
......@@ -202,34 +234,34 @@ LOAD c:/program files (x86)/gnu tools arm embedded/6.2 2016q4/bin/../lib/gcc/arm
*(.rodata*)
*(.eh_frame*)
.glue_7 0x00000094 0x0
.glue_7 0x00000094 0x0 linker stubs
.glue_7 0x08000110 0x0
.glue_7 0x08000110 0x0 linker stubs
.glue_7t 0x00000094 0x0
.glue_7t 0x00000094 0x0 linker stubs
.glue_7t 0x08000110 0x0
.glue_7t 0x08000110 0x0 linker stubs
.vfp11_veneer 0x00000094 0x0
.vfp11_veneer 0x00000094 0x0 linker stubs
.vfp11_veneer 0x08000110 0x0
.vfp11_veneer 0x08000110 0x0 linker stubs
.v4_bx 0x00000094 0x0
.v4_bx 0x00000094 0x0 linker stubs
.v4_bx 0x08000110 0x0
.v4_bx 0x08000110 0x0 linker stubs
.iplt 0x00000094 0x0
.iplt 0x00000094 0x0 c:/program files (x86)/gnu tools arm embedded/6.2 2016q4/bin/../lib/gcc/arm-none-eabi/6.2.1/thumb/v6-m/crtbegin.o
.iplt 0x08000110 0x0
.iplt 0x08000110 0x0 c:/program files (x86)/gnu tools arm embedded/6.2 2016q4/bin/../lib/gcc/arm-none-eabi/6.2.1/thumb/v6-m/crtbegin.o
.rel.dyn 0x00000094 0x0
.rel.iplt 0x00000094 0x0 c:/program files (x86)/gnu tools arm embedded/6.2 2016q4/bin/../lib/gcc/arm-none-eabi/6.2.1/thumb/v6-m/crtbegin.o
.rel.dyn 0x08000110 0x0
.rel.iplt 0x08000110 0x0 c:/program files (x86)/gnu tools arm embedded/6.2 2016q4/bin/../lib/gcc/arm-none-eabi/6.2.1/thumb/v6-m/crtbegin.o
.ARM.extab
*(.ARM.extab* .gnu.linkonce.armextab.*)
0x00000094 __exidx_start = .
0x08000110 __exidx_start = .
.ARM.exidx
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
0x00000094 __exidx_end = .
0x00000094 __etext = ALIGN (0x4)
0x08000110 __exidx_end = .
0x08000110 __etext = ALIGN (0x4)
.data 0x10000000 0x0 load address 0x00000094
.data 0x10000000 0x0 load address 0x08000110
0x10000000 __data_start__ = .
*(vtable)
*(.data*)
......@@ -266,15 +298,15 @@ LOAD c:/program files (x86)/gnu tools arm embedded/6.2 2016q4/bin/../lib/gcc/arm
0x10000000 __end__ = .
[!provide] PROVIDE (end, .)
*(.heap*)
.heap 0x10000000 0x0 C:\Users\Paul\AppData\Local\Temp\ccQBXc5q.o
.heap 0x10000000 0x0 C:\Users\Paul\AppData\Local\Temp\ccy2ub8W.o
0x10000000 __HeapLimit = .
.stack_dummy 0x10000000 0xc00
*(.stack*)
.stack 0x10000000 0xc00 C:\Users\Paul\AppData\Local\Temp\ccQBXc5q.o
0x10002000 __StackTop = (ORIGIN (RAM) + LENGTH (RAM))
0x10001400 __StackLimit = (__StackTop - SIZEOF (.stack_dummy))
0x10002000 PROVIDE (__stack, __StackTop)
.stack 0x10000000 0xc00 C:\Users\Paul\AppData\Local\Temp\ccy2ub8W.o
0x10010000 __StackTop = (ORIGIN (RAM) + LENGTH (RAM))
0x1000f400 __StackLimit = (__StackTop - SIZEOF (.stack_dummy))
0x10010000 PROVIDE (__stack, __StackTop)
0x00000001 ASSERT ((__StackLimit >= __HeapLimit), region RAM overflowed with stack)
OUTPUT(build/baremetal.elf elf32-littlearm)
......@@ -283,10 +315,10 @@ OUTPUT(build/baremetal.elf elf32-littlearm)
.ARM.attributes
0x00000000 0x1e c:/program files (x86)/gnu tools arm embedded/6.2 2016q4/bin/../lib/gcc/arm-none-eabi/6.2.1/thumb/v6-m/crti.o
.ARM.attributes
0x0000001e 0x1b C:\Users\Paul\AppData\Local\Temp\ccQBXc5q.o
0x0000001e 0x1b C:\Users\Paul\AppData\Local\Temp\ccy2ub8W.o
.ARM.attributes
0x00000039 0x2f C:\Users\Paul\AppData\Local\Temp\cc6fO4mu.ltrans0.ltrans.o
0x00000039 0x2f C:\Users\Paul\AppData\Local\Temp\ccg6fkcI.ltrans0.ltrans.o
.comment 0x00000000 0x6e
.comment 0x00000000 0x6e C:\Users\Paul\AppData\Local\Temp\cc6fO4mu.ltrans0.ltrans.o
.comment 0x00000000 0x6e C:\Users\Paul\AppData\Local\Temp\ccg6fkcI.ltrans0.ltrans.o
0x6f (size before relaxing)
/**************************************************************************//**
* @file cmsis_gcc.h
* @brief CMSIS Cortex-M Core Function/Instruction Header File
* @version V4.30
* @date 20. October 2015
******************************************************************************/
/* Copyright (c) 2009 - 2015 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#ifndef __CMSIS_GCC_H
#define __CMSIS_GCC_H
/* ignore some GCC warnings */
#if defined ( __GNUC__ )
#pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Wsign-conversion"
#pragma GCC diagnostic ignored "-Wconversion"
#pragma GCC diagnostic ignored "-Wunused-parameter"
#endif
/* ########################### Core Function Access ########################### */
/** \ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
@{
*/
/**
\brief Enable IRQ Interrupts
\details Enables IRQ interrupts by clearing the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
{
__ASM volatile ("cpsie i" : : : "memory");
}
/**
\brief Disable IRQ Interrupts
\details Disables IRQ interrupts by setting the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
{
__ASM volatile ("cpsid i" : : : "memory");
}
/**
\brief Get Control Register
\details Returns the content of the Control Register.
\return Control Register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
{
uint32_t result;
__ASM volatile ("MRS %0, control" : "=r" (result) );
return(result);
}
/**
\brief Set Control Register
\details Writes the given value to the Control Register.
\param [in] control Control Register value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
{
__ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
}
/**
\brief Get IPSR Register
\details Returns the content of the IPSR Register.
\return IPSR Register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
{
uint32_t result;
__ASM volatile ("MRS %0, ipsr" : "=r" (result) );
return(result);
}
/**
\brief Get APSR Register
\details Returns the content of the APSR Register.
\return APSR Register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
{
uint32_t result;
__ASM volatile ("MRS %0, apsr" : "=r" (result) );
return(result);
}
/**
\brief Get xPSR Register
\details Returns the content of the xPSR Register.
\return xPSR Register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
{
uint32_t result;
__ASM volatile ("MRS %0, xpsr" : "=r" (result) );
return(result);
}
/**
\brief Get Process Stack Pointer
\details Returns the current value of the Process Stack Pointer (PSP).
\return PSP Register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
{
register uint32_t result;
__ASM volatile ("MRS %0, psp\n" : "=r" (result) );
return(result);
}
/**
\brief Set Process Stack Pointer
\details Assigns the given value to the Process Stack Pointer (PSP).
\param [in] topOfProcStack Process Stack Pointer value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
{
__ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");
}
/**
\brief Get Main Stack Pointer
\details Returns the current value of the Main Stack Pointer (MSP).
\return MSP Register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
{
register uint32_t result;
__ASM volatile ("MRS %0, msp\n" : "=r" (result) );
return(result);
}
/**
\brief Set Main Stack Pointer
\details Assigns the given value to the Main Stack Pointer (MSP).
\param [in] topOfMainStack Main Stack Pointer value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
{
__ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");
}
/**
\brief Get Priority Mask
\details Returns the current state of the priority mask bit from the Priority Mask Register.
\return Priority Mask value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
{
uint32_t result;
__ASM volatile ("MRS %0, primask" : "=r" (result) );
return(result);
}
/**
\brief Set Priority Mask
\details Assigns the given value to the Priority Mask Register.
\param [in] priMask Priority Mask
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
{
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
}
#if (__CORTEX_M >= 0x03U)
/**
\brief Enable FIQ
\details Enables FIQ interrupts by clearing the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
{
__ASM volatile ("cpsie f" : : : "memory");
}
/**
\brief Disable FIQ
\details Disables FIQ interrupts by setting the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
{
__ASM volatile ("cpsid f" : : : "memory");
}
/**
\brief Get Base Priority
\details Returns the current value of the Base Priority register.
\return Base Priority register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
{
uint32_t result;
__ASM volatile ("MRS %0, basepri" : "=r" (result) );
return(result);
}
/**
\brief Set Base Priority
\details Assigns the given value to the Base Priority register.
\param [in] basePri Base Priority value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
{
__ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");
}
/**
\brief Set Base Priority with condition
\details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
or the new value increases the BASEPRI priority level.
\param [in] basePri Base Priority value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t value)
{
__ASM volatile ("MSR basepri_max, %0" : : "r" (value) : "memory");
}
/**
\brief Get Fault Mask
\details Returns the current value of the Fault Mask register.
\return Fault Mask register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
{
uint32_t result;
__ASM volatile ("MRS %0, faultmask" : "=r" (result) );
return(result);
}
/**
\brief Set Fault Mask
\details Assigns the given value to the Fault Mask register.
\param [in] faultMask Fault Mask value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
{
__ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
}
#endif /* (__CORTEX_M >= 0x03U) */
#if (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U)
/**
\brief Get FPSCR
\details Returns the current value of the Floating Point Status/Control register.
\return Floating Point Status/Control register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
{
#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)
uint32_t result;
/* Empty asm statement works as a scheduling barrier */
__ASM volatile ("");
__ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
__ASM volatile ("");
return(result);
#else
return(0);
#endif
}
/**
\brief Set FPSCR
\details Assigns the given value to the Floating Point Status/Control register.
\param [in] fpscr Floating Point Status/Control value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
{
#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)
/* Empty asm statement works as a scheduling barrier */
__ASM volatile ("");
__ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");
__ASM volatile ("");
#endif
}
#endif /* (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) */
/*@} end of CMSIS_Core_RegAccFunctions */
/* ########################## Core Instruction Access ######################### */
/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
Access to dedicated instructions
@{
*/
/* Define macros for porting to both thumb1 and thumb2.
* For thumb1, use low register (r0-r7), specified by constraint "l"
* Otherwise, use general registers, specified by constraint "r" */
#if defined (__thumb__) && !defined (__thumb2__)
#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
#define __CMSIS_GCC_USE_REG(r) "l" (r)
#else
#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
#define __CMSIS_GCC_USE_REG(r) "r" (r)
#endif
/**
\brief No Operation
\details No Operation does nothing. This instruction can be used for code alignment purposes.
*/
__attribute__((always_inline)) __STATIC_INLINE void __NOP(void)
{
__ASM volatile ("nop");
}
/**
\brief Wait For Interrupt
\details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
*/
__attribute__((always_inline)) __STATIC_INLINE void __WFI(void)
{
__ASM volatile ("wfi");
}
/**
\brief Wait For Event
\details Wait For Event is a hint instruction that permits the processor to enter
a low-power state until one of a number of events occurs.
*/
__attribute__((always_inline)) __STATIC_INLINE void __WFE(void)
{
__ASM volatile ("wfe");
}
/**
\brief Send Event
\details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
*/
__attribute__((always_inline)) __STATIC_INLINE void __SEV(void)
{
__ASM volatile ("sev");
}
/**
\brief Instruction Synchronization Barrier
\details Instruction Synchronization Barrier flushes the pipeline in the processor,
so that all instructions following the ISB are fetched from cache or memory,
after the instruction has been completed.
*/
__attribute__((always_inline)) __STATIC_INLINE void __ISB(void)
{
__ASM volatile ("isb 0xF":::"memory");
}
/**
\brief Data Synchronization Barrier
\details Acts as a special kind of Data Memory Barrier.
It completes when all explicit memory accesses before this instruction complete.
*/
__attribute__((always_inline)) __STATIC_INLINE void __DSB(void)
{
__ASM volatile ("dsb 0xF":::"memory");
}
/**
\brief Data Memory Barrier
\details Ensures the apparent order of the explicit memory operations before
and after the instruction, without ensuring their completion.
*/
__attribute__((always_inline)) __STATIC_INLINE void __DMB(void)
{
__ASM volatile ("dmb 0xF":::"memory");
}
/**
\brief Reverse byte order (32 bit)
\details Reverses the byte order in integer value.
\param [in] value Value to reverse
\return Reversed value
*/
__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value)
{
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
return __builtin_bswap32(value);
#else
uint32_t result;
__ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
return(result);
#endif
}
/**
\brief Reverse byte order (16 bit)
\details Reverses the byte order in two unsigned short values.
\param [in] value Value to reverse
\return Reversed value
*/
__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value)
{
uint32_t result;
__ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
return(result);
}
/**
\brief Reverse byte order in signed short value
\details Reverses the byte order in a signed short value with sign extension to integer.
\param [in] value Value to reverse
\return Reversed value
*/
__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value)
{