Commit 22a17230 by Paul Molloy

Have things finally working with switch input and LED outputs.

Issue was due to messed up SRAM define in linker script.  IDK what
datasheet I was reading..  But I had the location and size completely
wrong.  That caused any access of SRAM to cause a hardfault of course.
First happening when popping anything to the stack.  Which also explains
why I couldn't look at the stack to figure out the last called instruciton
to point to where the issue was...

copied stm32f0xx_*.h files over from STM32F0xx_StdPeriph_Driver/inc dir
parent 7254f4b5
......@@ -34,7 +34,7 @@ ARCH_FLAGS=-mthumb -mcpu=cortex-m$(CORTEX_M)
STARTUP=$(BASE)/startup/startup_ARM$(CORE).S
# -Os -flto -ffunction-sections -fdata-sections to compile for code size
CFLAGS=$(ARCH_FLAGS) $(STARTUP_DEFS) -Os -flto -ffunction-sections -fdata-sections
CFLAGS=$(ARCH_FLAGS) $(STARTUP_DEFS) -Os -flto -ffunction-sections -fdata-sections -g
CXXFLAGS=$(CFLAGS)
# Link for code size
......@@ -43,7 +43,7 @@ GC=-Wl,--gc-sections
# Create map file
MAP=-Wl,-Map=$(BUILD)/$(PROJ).map
STARTUP_DEFS=-D__STARTUP_CLEAR_BSS -D__START=main
STARTUP_DEFS=-D__STARTUP_CLEAR_BSS -D__START=main -D__NO_SYSTEM_INIT
LDSCRIPTS=-L. -L$(BASE)/ldscripts -T nokeep.ld
LFLAGS=$(USE_NANO) $(USE_NOHOST) $(LDSCRIPTS) $(GC) $(MAP)
......@@ -57,8 +57,8 @@ CFLAGS+= $(DEFINE) $(INCLUDE)
SOURCES=$(wildcard source/**/*.c source/*.c)
OBJECTS=$(patsubst %.c,%.o,$(SOURCES))
all: dir $(BUILD)/$(PROJ).axf $(BUILD)/$(PROJ).elf $(BUILD)/$(PROJ).hex $(BUILD)/$(PROJ).bin size
#all: dir $(BUILD)/$(PROJ).elf $(BUILD)/$(PROJ).hex $(BUILD)/$(PROJ).bin size
#all: dir $(BUILD)/$(PROJ).axf $(BUILD)/$(PROJ).elf $(BUILD)/$(PROJ).hex $(BUILD)/$(PROJ).bin size
all: dir $(BUILD)/$(PROJ).elf $(BUILD)/$(PROJ).hex $(BUILD)/$(PROJ).bin size
#build axf file output (basically elf with DWARF debug info)
# $@ is shortcut for the target, $^ is shortcut for prereqs
......@@ -81,6 +81,9 @@ dir:
size: $(BUILD)/$(PROJ).elf
$(SIZE) -t $^
disassm:
arm-none-eabi-objdump build\baremetal.elf -d -g
clean:
rm -rf $(BUILD)
rm -f $(OBJECTS)
/**
******************************************************************************
* @file stm32f0xx_gpio.h
* @author MCD Application Team
* @version V1.5.0
* @date 05-December-2014
* @brief This file contains all the functions prototypes for the GPIO
* firmware library.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F0XX_GPIO_H
#define __STM32F0XX_GPIO_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f0xx.h"
/** @addtogroup STM32F0xx_StdPeriph_Driver
* @{
*/
/** @addtogroup GPIO
* @{
*/
/* Exported types ------------------------------------------------------------*/
#define IS_GPIO_ALL_PERIPH(PERIPH) (((PERIPH) == GPIOA) || \
((PERIPH) == GPIOB) || \
((PERIPH) == GPIOC) || \
((PERIPH) == GPIOD) || \
((PERIPH) == GPIOE) || \
((PERIPH) == GPIOF))
#define IS_GPIO_LIST_PERIPH(PERIPH) (((PERIPH) == GPIOA) || \
((PERIPH) == GPIOB))
/** @defgroup Configuration_Mode_enumeration
* @{
*/
typedef enum
{
GPIO_Mode_IN = 0x00, /*!< GPIO Input Mode */
GPIO_Mode_OUT = 0x01, /*!< GPIO Output Mode */
GPIO_Mode_AF = 0x02, /*!< GPIO Alternate function Mode */
GPIO_Mode_AN = 0x03 /*!< GPIO Analog In/Out Mode */
}GPIOMode_TypeDef;
#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_Mode_IN)|| ((MODE) == GPIO_Mode_OUT) || \
((MODE) == GPIO_Mode_AF)|| ((MODE) == GPIO_Mode_AN))
/**
* @}
*/
/** @defgroup Output_type_enumeration
* @{
*/
typedef enum
{
GPIO_OType_PP = 0x00,
GPIO_OType_OD = 0x01
}GPIOOType_TypeDef;
#define IS_GPIO_OTYPE(OTYPE) (((OTYPE) == GPIO_OType_PP) || ((OTYPE) == GPIO_OType_OD))
/**
* @}
*/
/** @defgroup Output_Maximum_frequency_enumeration
* @{
*/
typedef enum
{
GPIO_Speed_Level_1 = 0x00, /*!< I/O output speed: Low 2 MHz */
GPIO_Speed_Level_2 = 0x01, /*!< I/O output speed: Medium 10 MHz */
GPIO_Speed_Level_3 = 0x03 /*!< I/O output speed: High 50 MHz */
}GPIOSpeed_TypeDef;
#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_Speed_Level_1) || ((SPEED) == GPIO_Speed_Level_2) || \
((SPEED) == GPIO_Speed_Level_3))
/**
* @}
*/
/** @defgroup Configuration_Pull-Up_Pull-Down_enumeration
* @{
*/
typedef enum
{
GPIO_PuPd_NOPULL = 0x00,
GPIO_PuPd_UP = 0x01,
GPIO_PuPd_DOWN = 0x02
}GPIOPuPd_TypeDef;
#define IS_GPIO_PUPD(PUPD) (((PUPD) == GPIO_PuPd_NOPULL) || ((PUPD) == GPIO_PuPd_UP) || \
((PUPD) == GPIO_PuPd_DOWN))
/**
* @}
*/
/** @defgroup Bit_SET_and_Bit_RESET_enumeration
* @{
*/
typedef enum
{
Bit_RESET = 0,
Bit_SET
}BitAction;
#define IS_GPIO_BIT_ACTION(ACTION) (((ACTION) == Bit_RESET) || ((ACTION) == Bit_SET))
/**
* @}
*/
/**
* @brief GPIO Init structure definition
*/
typedef struct
{
uint32_t GPIO_Pin; /*!< Specifies the GPIO pins to be configured.
This parameter can be any value of @ref GPIO_pins_define */
GPIOMode_TypeDef GPIO_Mode; /*!< Specifies the operating mode for the selected pins.
This parameter can be a value of @ref GPIOMode_TypeDef */
GPIOSpeed_TypeDef GPIO_Speed; /*!< Specifies the speed for the selected pins.
This parameter can be a value of @ref GPIOSpeed_TypeDef */
GPIOOType_TypeDef GPIO_OType; /*!< Specifies the operating output type for the selected pins.
This parameter can be a value of @ref GPIOOType_TypeDef */
GPIOPuPd_TypeDef GPIO_PuPd; /*!< Specifies the operating Pull-up/Pull down for the selected pins.
This parameter can be a value of @ref GPIOPuPd_TypeDef */
}GPIO_InitTypeDef;
/* Exported constants --------------------------------------------------------*/
/** @defgroup GPIO_Exported_Constants
* @{
*/
/** @defgroup GPIO_pins_define
* @{
*/
#define GPIO_Pin_0 ((uint16_t)0x0001) /*!< Pin 0 selected */
#define GPIO_Pin_1 ((uint16_t)0x0002) /*!< Pin 1 selected */
#define GPIO_Pin_2 ((uint16_t)0x0004) /*!< Pin 2 selected */
#define GPIO_Pin_3 ((uint16_t)0x0008) /*!< Pin 3 selected */
#define GPIO_Pin_4 ((uint16_t)0x0010) /*!< Pin 4 selected */
#define GPIO_Pin_5 ((uint16_t)0x0020) /*!< Pin 5 selected */
#define GPIO_Pin_6 ((uint16_t)0x0040) /*!< Pin 6 selected */
#define GPIO_Pin_7 ((uint16_t)0x0080) /*!< Pin 7 selected */
#define GPIO_Pin_8 ((uint16_t)0x0100) /*!< Pin 8 selected */
#define GPIO_Pin_9 ((uint16_t)0x0200) /*!< Pin 9 selected */
#define GPIO_Pin_10 ((uint16_t)0x0400) /*!< Pin 10 selected */
#define GPIO_Pin_11 ((uint16_t)0x0800) /*!< Pin 11 selected */
#define GPIO_Pin_12 ((uint16_t)0x1000) /*!< Pin 12 selected */
#define GPIO_Pin_13 ((uint16_t)0x2000) /*!< Pin 13 selected */
#define GPIO_Pin_14 ((uint16_t)0x4000) /*!< Pin 14 selected */
#define GPIO_Pin_15 ((uint16_t)0x8000) /*!< Pin 15 selected */
#define GPIO_Pin_All ((uint16_t)0xFFFF) /*!< All pins selected */
#define IS_GPIO_PIN(PIN) ((PIN) != (uint16_t)0x00)
#define IS_GET_GPIO_PIN(PIN) (((PIN) == GPIO_Pin_0) || \
((PIN) == GPIO_Pin_1) || \
((PIN) == GPIO_Pin_2) || \
((PIN) == GPIO_Pin_3) || \
((PIN) == GPIO_Pin_4) || \
((PIN) == GPIO_Pin_5) || \
((PIN) == GPIO_Pin_6) || \
((PIN) == GPIO_Pin_7) || \
((PIN) == GPIO_Pin_8) || \
((PIN) == GPIO_Pin_9) || \
((PIN) == GPIO_Pin_10) || \
((PIN) == GPIO_Pin_11) || \
((PIN) == GPIO_Pin_12) || \
((PIN) == GPIO_Pin_13) || \
((PIN) == GPIO_Pin_14) || \
((PIN) == GPIO_Pin_15))
/**
* @}
*/
/** @defgroup GPIO_Pin_sources
* @{
*/
#define GPIO_PinSource0 ((uint8_t)0x00)
#define GPIO_PinSource1 ((uint8_t)0x01)
#define GPIO_PinSource2 ((uint8_t)0x02)
#define GPIO_PinSource3 ((uint8_t)0x03)
#define GPIO_PinSource4 ((uint8_t)0x04)
#define GPIO_PinSource5 ((uint8_t)0x05)
#define GPIO_PinSource6 ((uint8_t)0x06)
#define GPIO_PinSource7 ((uint8_t)0x07)
#define GPIO_PinSource8 ((uint8_t)0x08)
#define GPIO_PinSource9 ((uint8_t)0x09)
#define GPIO_PinSource10 ((uint8_t)0x0A)
#define GPIO_PinSource11 ((uint8_t)0x0B)
#define GPIO_PinSource12 ((uint8_t)0x0C)
#define GPIO_PinSource13 ((uint8_t)0x0D)
#define GPIO_PinSource14 ((uint8_t)0x0E)
#define GPIO_PinSource15 ((uint8_t)0x0F)
#define IS_GPIO_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == GPIO_PinSource0) || \
((PINSOURCE) == GPIO_PinSource1) || \
((PINSOURCE) == GPIO_PinSource2) || \
((PINSOURCE) == GPIO_PinSource3) || \
((PINSOURCE) == GPIO_PinSource4) || \
((PINSOURCE) == GPIO_PinSource5) || \
((PINSOURCE) == GPIO_PinSource6) || \
((PINSOURCE) == GPIO_PinSource7) || \
((PINSOURCE) == GPIO_PinSource8) || \
((PINSOURCE) == GPIO_PinSource9) || \
((PINSOURCE) == GPIO_PinSource10) || \
((PINSOURCE) == GPIO_PinSource11) || \
((PINSOURCE) == GPIO_PinSource12) || \
((PINSOURCE) == GPIO_PinSource13) || \
((PINSOURCE) == GPIO_PinSource14) || \
((PINSOURCE) == GPIO_PinSource15))
/**
* @}
*/
/** @defgroup GPIO_Alternate_function_selection_define
* @{
*/
/**
* @brief AF 0 selection
*/
#define GPIO_AF_0 ((uint8_t)0x00) /* WKUP, EVENTOUT, TIM15, SPI1, TIM17,
MCO, SWDAT, SWCLK, TIM14, BOOT,
USART1, CEC, IR_OUT, SPI2, TS, TIM3,
USART4, CAN, TIM3, USART2, USART3,
CRS, TIM16, TIM1 */
/**
* @brief AF 1 selection
*/
#define GPIO_AF_1 ((uint8_t)0x01) /* USART2, CEC, TIM3, USART1, IR,
EVENTOUT, I2C1, I2C2, TIM15, SPI2,
USART3, TS, SPI1 */
/**
* @brief AF 2 selection
*/
#define GPIO_AF_2 ((uint8_t)0x02) /* TIM2, TIM1, EVENTOUT, TIM16, TIM17,
USB */
/**
* @brief AF 3 selection
*/
#define GPIO_AF_3 ((uint8_t)0x03) /* TS, I2C1, TIM15, EVENTOUT */
/**
* @brief AF 4 selection
*/
#define GPIO_AF_4 ((uint8_t)0x04) /* TIM14, USART4, USART3, CRS, CAN,
I2C1 */
/**
* @brief AF 5 selection
*/
#define GPIO_AF_5 ((uint8_t)0x05) /* TIM16, TIM17, TIM15, SPI2, I2C2,
MCO, I2C1, USB */
/**
* @brief AF 6 selection
*/
#define GPIO_AF_6 ((uint8_t)0x06) /* EVENTOUT */
/**
* @brief AF 7 selection
*/
#define GPIO_AF_7 ((uint8_t)0x07) /* COMP1 OUT and COMP2 OUT */
#define IS_GPIO_AF(AF) (((AF) == GPIO_AF_0) || ((AF) == GPIO_AF_1) || \
((AF) == GPIO_AF_2) || ((AF) == GPIO_AF_3) || \
((AF) == GPIO_AF_4) || ((AF) == GPIO_AF_5) || \
((AF) == GPIO_AF_6) || ((AF) == GPIO_AF_7))
/**
* @}
*/
/** @defgroup GPIO_Speed_Legacy
* @{
*/
#define GPIO_Speed_2MHz GPIO_Speed_Level_1 /*!< I/O output speed: Low 2 MHz */
#define GPIO_Speed_10MHz GPIO_Speed_Level_2 /*!< I/O output speed: Medium 10 MHz */
#define GPIO_Speed_50MHz GPIO_Speed_Level_3 /*!< I/O output speed: High 50 MHz */
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
/* Function used to set the GPIO configuration to the default reset state *****/
void GPIO_DeInit(GPIO_TypeDef* GPIOx);
/* Initialization and Configuration functions *********************************/
void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct);
void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct);
void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
/* GPIO Read and Write functions **********************************************/
uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx);
uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx);
void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal);
void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal);
/* GPIO Alternate functions configuration functions ***************************/
void GPIO_PinAFConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_PinSource, uint8_t GPIO_AF);
#ifdef __cplusplus
}
#endif
#endif /* __STM32F0XX_GPIO_H */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
/**
******************************************************************************
* @file stm32f0xx_rcc.h
* @author MCD Application Team
* @version V1.5.0
* @date 05-December-2014
* @brief This file contains all the functions prototypes for the RCC
* firmware library.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F0XX_RCC_H
#define __STM32F0XX_RCC_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f0xx.h"
/** @addtogroup STM32F0xx_StdPeriph_Driver
* @{
*/
/** @addtogroup RCC
* @{
*/
/* Exported types ------------------------------------------------------------*/
typedef struct
{
uint32_t SYSCLK_Frequency;
uint32_t HCLK_Frequency;
uint32_t PCLK_Frequency;
uint32_t ADCCLK_Frequency;
uint32_t CECCLK_Frequency;
uint32_t I2C1CLK_Frequency;
uint32_t USART1CLK_Frequency;
uint32_t USART2CLK_Frequency; /*!< Only applicable for STM32F072 and STM32F091 devices */
uint32_t USART3CLK_Frequency; /*!< Only applicable for STM32F091 devices */
uint32_t USBCLK_Frequency; /*!< Only applicable for STM32F072 devices */
}RCC_ClocksTypeDef;
/* Exported constants --------------------------------------------------------*/
/** @defgroup RCC_Exported_Constants
* @{
*/
/** @defgroup RCC_HSE_configuration
* @{
*/
#define RCC_HSE_OFF ((uint8_t)0x00)
#define RCC_HSE_ON ((uint8_t)0x01)
#define RCC_HSE_Bypass ((uint8_t)0x05)
#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \
((HSE) == RCC_HSE_Bypass))
/**
* @}
*/
/** @defgroup RCC_PLL_Clock_Source
* @{
*/
#define RCC_PLLSource_HSI_Div2 RCC_CFGR_PLLSRC_HSI_Div2
#define RCC_PLLSource_PREDIV1 RCC_CFGR_PLLSRC_HSE_PREDIV /* Old HSEPREDIV1 bit definition, maintained for legacy purpose */
#define RCC_PLLSource_HSE RCC_CFGR_PLLSRC_HSE_PREDIV /*!< Only applicable for STM32F072 devices */
#define RCC_PLLSource_HSI48 RCC_CFGR_PLLSRC_HSI48_PREDIV /*!< Only applicable for STM32F072 devices */
#define RCC_PLLSource_HSI RCC_CFGR_PLLSRC_HSI_PREDIV /*!< Only applicable for STM32F072 devices */
#define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI_Div2) || \
((SOURCE) == RCC_PLLSource_HSI48) || \
((SOURCE) == RCC_PLLSource_HSI) || \
((SOURCE) == RCC_PLLSource_HSE) || \
((SOURCE) == RCC_PLLSource_PREDIV1))
/**
* @}
*/
/** @defgroup RCC_PLL_Multiplication_Factor
* @{
*/
#define RCC_PLLMul_2 RCC_CFGR_PLLMULL2
#define RCC_PLLMul_3 RCC_CFGR_PLLMULL3
#define RCC_PLLMul_4 RCC_CFGR_PLLMULL4
#define RCC_PLLMul_5 RCC_CFGR_PLLMULL5
#define RCC_PLLMul_6 RCC_CFGR_PLLMULL6
#define RCC_PLLMul_7 RCC_CFGR_PLLMULL7
#define RCC_PLLMul_8 RCC_CFGR_PLLMULL8
#define RCC_PLLMul_9 RCC_CFGR_PLLMULL9
#define RCC_PLLMul_10 RCC_CFGR_PLLMULL10
#define RCC_PLLMul_11 RCC_CFGR_PLLMULL11
#define RCC_PLLMul_12 RCC_CFGR_PLLMULL12
#define RCC_PLLMul_13 RCC_CFGR_PLLMULL13
#define RCC_PLLMul_14 RCC_CFGR_PLLMULL14
#define RCC_PLLMul_15 RCC_CFGR_PLLMULL15
#define RCC_PLLMul_16 RCC_CFGR_PLLMULL16
#define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLLMul_2) || ((MUL) == RCC_PLLMul_3) || \
((MUL) == RCC_PLLMul_4) || ((MUL) == RCC_PLLMul_5) || \
((MUL) == RCC_PLLMul_6) || ((MUL) == RCC_PLLMul_7) || \
((MUL) == RCC_PLLMul_8) || ((MUL) == RCC_PLLMul_9) || \
((MUL) == RCC_PLLMul_10) || ((MUL) == RCC_PLLMul_11) || \
((MUL) == RCC_PLLMul_12) || ((MUL) == RCC_PLLMul_13) || \
((MUL) == RCC_PLLMul_14) || ((MUL) == RCC_PLLMul_15) || \
((MUL) == RCC_PLLMul_16))
/**
* @}
*/
/** @defgroup RCC_PREDIV1_division_factor
* @{
*/
#define RCC_PREDIV1_Div1 RCC_CFGR2_PREDIV1_DIV1
#define RCC_PREDIV1_Div2 RCC_CFGR2_PREDIV1_DIV2
#define RCC_PREDIV1_Div3 RCC_CFGR2_PREDIV1_DIV3
#define RCC_PREDIV1_Div4 RCC_CFGR2_PREDIV1_DIV4
#define RCC_PREDIV1_Div5 RCC_CFGR2_PREDIV1_DIV5
#define RCC_PREDIV1_Div6 RCC_CFGR2_PREDIV1_DIV6
#define RCC_PREDIV1_Div7 RCC_CFGR2_PREDIV1_DIV7
#define RCC_PREDIV1_Div8 RCC_CFGR2_PREDIV1_DIV8
#define RCC_PREDIV1_Div9 RCC_CFGR2_PREDIV1_DIV9
#define RCC_PREDIV1_Div10 RCC_CFGR2_PREDIV1_DIV10
#define RCC_PREDIV1_Div11 RCC_CFGR2_PREDIV1_DIV11
#define RCC_PREDIV1_Div12 RCC_CFGR2_PREDIV1_DIV12
#define RCC_PREDIV1_Div13 RCC_CFGR2_PREDIV1_DIV13
#define RCC_PREDIV1_Div14 RCC_CFGR2_PREDIV1_DIV14
#define RCC_PREDIV1_Div15 RCC_CFGR2_PREDIV1_DIV15
#define RCC_PREDIV1_Div16 RCC_CFGR2_PREDIV1_DIV16
#define IS_RCC_PREDIV1(PREDIV1) (((PREDIV1) == RCC_PREDIV1_Div1) || ((PREDIV1) == RCC_PREDIV1_Div2) || \
((PREDIV1) == RCC_PREDIV1_Div3) || ((PREDIV1) == RCC_PREDIV1_Div4) || \
((PREDIV1) == RCC_PREDIV1_Div5) || ((PREDIV1) == RCC_PREDIV1_Div6) || \
((PREDIV1) == RCC_PREDIV1_Div7) || ((PREDIV1) == RCC_PREDIV1_Div8) || \
((PREDIV1) == RCC_PREDIV1_Div9) || ((PREDIV1) == RCC_PREDIV1_Div10) || \
((PREDIV1) == RCC_PREDIV1_Div11) || ((PREDIV1) == RCC_PREDIV1_Div12) || \
((PREDIV1) == RCC_PREDIV1_Div13) || ((PREDIV1) == RCC_PREDIV1_Div14) || \
((PREDIV1) == RCC_PREDIV1_Div15) || ((PREDIV1) == RCC_PREDIV1_Div16))
/**
* @}
*/
/** @defgroup RCC_System_Clock_Source
* @{
*/
#define RCC_SYSCLKSource_HSI RCC_CFGR_SW_HSI
#define RCC_SYSCLKSource_HSE RCC_CFGR_SW_HSE
#define RCC_SYSCLKSource_PLLCLK RCC_CFGR_SW_PLL
#define RCC_SYSCLKSource_HSI48 RCC_CFGR_SW_HSI48 /*!< Only applicable for STM32F072 devices */
#define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \
((SOURCE) == RCC_SYSCLKSource_HSE) || \
((SOURCE) == RCC_SYSCLKSource_HSI48) || \
((SOURCE) == RCC_SYSCLKSource_PLLCLK))
/**
* @}
*/
/** @defgroup RCC_AHB_Clock_Source
* @{
*/
#define RCC_SYSCLK_Div1 RCC_CFGR_HPRE_DIV1
#define RCC_SYSCLK_Div2 RCC_CFGR_HPRE_DIV2
#define RCC_SYSCLK_Div4 RCC_CFGR_HPRE_DIV4
#define RCC_SYSCLK_Div8 RCC_CFGR_HPRE_DIV8
#define RCC_SYSCLK_Div16 RCC_CFGR_HPRE_DIV16
#define RCC_SYSCLK_Div64 RCC_CFGR_HPRE_DIV64
#define RCC_SYSCLK_Div128 RCC_CFGR_HPRE_DIV128
#define RCC_SYSCLK_Div256 RCC_CFGR_HPRE_DIV256
#define RCC_SYSCLK_Div512 RCC_CFGR_HPRE_DIV512
#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_Div1) || ((HCLK) == RCC_SYSCLK_Div2) || \
((HCLK) == RCC_SYSCLK_Div4) || ((HCLK) == RCC_SYSCLK_Div8) || \
((HCLK) == RCC_SYSCLK_Div16) || ((HCLK) == RCC_SYSCLK_Div64) || \
((HCLK) == RCC_SYSCLK_Div128) || ((HCLK) == RCC_SYSCLK_Div256) || \
((HCLK) == RCC_SYSCLK_Div512))
/**
* @}
*/
/** @defgroup RCC_APB_Clock_Source
* @{
*/
#define RCC_HCLK_Div1 RCC_CFGR_PPRE_DIV1
#define RCC_HCLK_Div2 RCC_CFGR_PPRE_DIV2
#define RCC_HCLK_Div4 RCC_CFGR_PPRE_DIV4
#define RCC_HCLK_Div8 RCC_CFGR_PPRE_DIV8
#define RCC_HCLK_Div16 RCC_CFGR_PPRE_DIV16
#define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_Div1) || ((PCLK) == RCC_HCLK_Div2) || \
((PCLK) == RCC_HCLK_Div4) || ((PCLK) == RCC_HCLK_Div8) || \
((PCLK) == RCC_HCLK_Div16))
/**
* @}
*/
/** @defgroup RCC_ADC_clock_source
* @{
*/
/* These defines are obsolete and kept for legacy purpose only.
Proper ADC clock selection is done within ADC driver by mean of the ADC_ClockModeConfig() function */
#define RCC_ADCCLK_HSI14 ((uint32_t)0x00000000)
#define RCC_ADCCLK_PCLK_Div2 ((uint32_t)0x01000000)
#define RCC_ADCCLK_PCLK_Div4 ((uint32_t)0x01004000)
#define IS_RCC_ADCCLK(ADCCLK) (((ADCCLK) == RCC_ADCCLK_HSI14) || ((ADCCLK) == RCC_ADCCLK_PCLK_Div2) || \
((ADCCLK) == RCC_ADCCLK_PCLK_Div4))
/**
* @}
*/
/** @defgroup RCC_CEC_clock_source
* @{
*/
#define RCC_CECCLK_HSI_Div244 ((uint32_t)0x00000000)
#define RCC_CECCLK_LSE RCC_CFGR3_CECSW
#define IS_RCC_CECCLK(CECCLK) (((CECCLK) == RCC_CECCLK_HSI_Div244) || ((CECCLK) == RCC_CECCLK_LSE))
/**
* @}
*/
/** @defgroup RCC_I2C_clock_source
* @{
*/
#define RCC_I2C1CLK_HSI ((uint32_t)0x00000000)
#define RCC_I2C1CLK_SYSCLK RCC_CFGR3_I2C1SW
#define IS_RCC_I2CCLK(I2CCLK) (((I2CCLK) == RCC_I2C1CLK_HSI) || ((I2CCLK) == RCC_I2C1CLK_SYSCLK))
/**
* @}
*/
/** @defgroup RCC_USB_clock_source
* @brief Applicable only for STM32F072 devices
* @{
*/
#define RCC_USBCLK_HSI48 ((uint32_t)0x00000000)
#define RCC_USBCLK_PLLCLK RCC_CFGR3_USBSW
#define IS_RCC_USBCLK(USBCLK) (((USBCLK) == RCC_USBCLK_HSI48) || ((USBCLK) == RCC_USBCLK_PLLCLK))
/**
* @}
*/
/** @defgroup RCC_USART_clock_source
* @{
*/
#define RCC_USART1CLK_PCLK ((uint32_t)0x10000000)
#define RCC_USART1CLK_SYSCLK ((uint32_t)0x10000001)
#define RCC_USART1CLK_LSE ((uint32_t)0x10000002)
#define RCC_USART1CLK_HSI ((uint32_t)0x10000003)
#define RCC_USART2CLK_PCLK ((uint32_t)0x20000000) /*!< Only applicable for STM32F072 and STM32F091 devices */
#define RCC_USART2CLK_SYSCLK ((uint32_t)0x20010000) /*!< Only applicable for STM32F072 and STM32F091 devices */
#define RCC_USART2CLK_LSE ((uint32_t)0x20020000) /*!< Only applicable for STM32F072 and STM32F091 devices */
#define RCC_USART2CLK_HSI ((uint32_t)0x20030000) /*!< Only applicable for STM32F072 and STM32F091 devices */
#define RCC_USART3CLK_PCLK ((uint32_t)0x30000000) /*!< Only applicable for STM32F091 devices */
#define RCC_USART3CLK_SYSCLK ((uint32_t)0x30040000) /*!< Only applicable for STM32F091 devices */
#define RCC_USART3CLK_LSE ((uint32_t)0x30080000) /*!< Only applicable for STM32F091 devices */
#define RCC_USART3CLK_HSI ((uint32_t)0x300C0000) /*!< Only applicable for STM32F091 devices */
#define IS_RCC_USARTCLK(USARTCLK) (((USARTCLK) == RCC_USART1CLK_PCLK) || \
((USARTCLK) == RCC_USART1CLK_SYSCLK) || \
((USARTCLK) == RCC_USART1CLK_LSE) || \
((USARTCLK) == RCC_USART1CLK_HSI) || \
((USARTCLK) == RCC_USART2CLK_PCLK) || \
((USARTCLK) == RCC_USART2CLK_SYSCLK) || \
((USARTCLK) == RCC_USART2CLK_LSE) || \
((USARTCLK) == RCC_USART2CLK_HSI)|| \
((USARTCLK) == RCC_USART3CLK_PCLK) || \
((USARTCLK) == RCC_USART3CLK_SYSCLK) || \
((USARTCLK) == RCC_USART3CLK_LSE) || \
((USARTCLK) == RCC_USART3CLK_HSI))
/**
* @}
*/
/** @defgroup RCC_Interrupt_Source
* @{
*/
#define RCC_IT_LSIRDY ((uint8_t)0x01)
#define RCC_IT_LSERDY ((uint8_t)0x02)
#define RCC_IT_HSIRDY ((uint8_t)0x04)
#define RCC_IT_HSERDY ((uint8_t)0x08)
#define RCC_IT_PLLRDY ((uint8_t)0x10)
#define RCC_IT_HSI14RDY ((uint8_t)0x20)
#define RCC_IT_HSI48RDY ((uint8_t)0x40) /*!< Only applicable for STM32F072 devices */
#define RCC_IT_CSS ((uint8_t)0x80)
#define IS_RCC_IT(IT) ((((IT) & (uint8_t)0x80) == 0x00) && ((IT) != 0x00))
#define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \
((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \
((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_HSI14RDY) || \
((IT) == RCC_IT_CSS) || ((IT) == RCC_IT_HSI48RDY))
#define IS_RCC_CLEAR_IT(IT) ((IT) != 0x00)
/**
* @}
*/
/** @defgroup RCC_LSE_Configuration
* @{
*/
#define RCC_LSE_OFF ((uint32_t)0x00000000)
#define RCC_LSE_ON RCC_BDCR_LSEON
#define RCC_LSE_Bypass ((uint32_t)(RCC_BDCR_LSEON | RCC_BDCR_LSEBYP))
#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \
((LSE) == RCC_LSE_Bypass))
/**
* @}
*/
/** @defgroup RCC_RTC_Clock_Source
* @{
*/
#define RCC_RTCCLKSource_LSE RCC_BDCR_RTCSEL_LSE
#define RCC_RTCCLKSource_LSI RCC_BDCR_RTCSEL_LSI
#define RCC_RTCCLKSource_HSE_Div32 RCC_BDCR_RTCSEL_HSE
#define IS_RCC_RTCCLK_SOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSource_LSE) || \
((SOURCE) == RCC_RTCCLKSource_LSI) || \
((SOURCE) == RCC_RTCCLKSource_HSE_Div32))
/**
* @}
*/