Allow assertion statements within the definition of composite types

As commented in #80 and #81:

#81 (comment 570502418)

I think the following, inspired by psl comments, is nice. It can be extended to --assert tdata'direction = to or similar checks. Moreover, it is easy for backwards compatibility:

type axis_t is record
  tdata : std_logic_vector;
  tkeep : std_logic_vector;
  --assert tdata'length/8 = tkeep'length
end record axis_t;

#80 (comment 570559123)

@umarcor I like the idea of using PSL syntax here - without the comment notation.

The comment notation that is only there because some simulators prefer not to support the syntax. If they want to do that, they can at least train themselves to ignore it without it having to be a comment.

#80 (comment 573012883)

The comment notation that is only there because some simulators prefer not to support the syntax. If they want to do that, they can at least train themselves to ignore it without it having to be a comment.

Some? All commercial simulators (I know). I only know GHDL supporting the correct syntax. I also like the idea of PSL in that context, but maybe it would be easier to allow plain VHDL asserts there. They are supported by all simulators I know.