Use "private" keyword in type declaration to prevent objects of this type.

Allow the use of the VHDL 2019 private keyword in type declarations, preventing creating objects of this type directly. A user then must use a defined subtype:

eg:

type axis_t is private record
  tdata : std_logic_vector;
  tkeep : std_logic_vector;
  --etc
end record axis_t;

signal s1 : axis_t(tdata(63 downto 0), tkeep(7 downto 0));  -- ilegal and compiler error;

subtype axis_64_t is axis_t(tdata(63 downto 0), tkeep(7 downto 0));

signal s2 : axis_64_t;  -- legal

private should also be available in subtypes if a user wanted to create a partially constrained version of the base type, but still require a fully constrained final version.

On an interface list, a user can still use a private type, as the object connected will always be a legal subtype.