Allow types/subtypes to have a defined range direction with no defined range limits

While VHDL 2019 added range records, I dont think it added the ability to partially constrain a subtype to a specify a direction but leave the direction open.

I propose "open" be allowed in the range bounds of a subtype:

subtype bv_descending_t is bit_vector(open downto open);

This would carry into interface definitions, where unconstrained items are allowed. This would remoove the need for for the current workaround of generics, assertions or normalisation alias to enforce a specified direction:

entity some_ent is
  port (
    desc_port : std_logic_vector(open downto open)
  )

Connecting an ascending array woould lead to a syntax error. The workaround above all require elaboration to find an error.