Arrays with Per Element Sizes (Heterogeneous Arrays)

Is your capability/feature request related to a problem?

Real hardware frequently contains collections of signals with different widths:

• instruction fields
• bus fabrics
• register files and blocks
• mixed‑width data-paths and generatable structures

VHDL currently requires all array elements to share the same subtype, which forces:

• use of record types, flattened vectors with manual slicing or individual signals.
• loss of indexability, error‑prone aliasing
• verbose, hard‑to‑maintain code

Describe the solution you'd like

type slv_array is array (natural range <>) of std_logic_vector;
constant bus_widths : integer_vector := (16, 4, 32, others => 8); -- defined like an aggregate
signal buses : slv_array(0 to 3)(bus_widths);

-- may want to support ranges i.e:
bus_ranges_1 : range_vector (16 downto 2, 4 downto 0, 32 downto 4, others => 8 downto 0);
signal buses_1 : slv_array(0 to 3)(bus_ranges_1);

bus_ranges_2 : range_vector (0 => 16 downto 2, 1 => 4 downto 0, 3=> 32 downto 4, others => 8 downto 0);
signal buses_2 : slv_array(0 to 3)(bus_ranges_2);

Describe alternatives you've considered

Additional context

There range_vector should be calculatable, so the higher level can use functions, i.e. in loops to assign the widths based on other constants.