std.env.resolution_limit - allow this to be more than "a secondary unit of type TIME"
Is your capability/feature request related to a problem?
This isn't much of a problem, just an odd inconsistency that simulator writers probably ignore.
5.2.4.2 says "An implementation may allow a given elaboration of a model ... to select a secondary unit of type TIME as the resolution limit," which I think means that the resolution limit (and the value returned by the function std.env.resolution_limit) can be:
1 fs, 1 ps, 1 ns, etc. and no other values are allowed.
I typically do mixed SystemVerilog / VHDL designs and simulations.
From IEEE Std 1800-2017 section 22.7 'timescale:
The integers in these arguments specify an order of magnitude for the size of the value; the valid integers are 1, 10, and 100. The character strings represent units of measurement; the valid character strings are s, ms, us, ns, ps, and fs.That means that in SystemVerilog the time_precision can be 1 fs, 10 fs, 100 fs, 1 ns, 10 ns, etc.
I typically use Modelsim; it allows the simulator time resolution (= the resolution limit) to be set from the command line as e.g. vsim -t 100ps work.my_design
I would want std.env.resolution_limit to return 100 ps for this example, yet the LRM doesn't explicitly allow that.
Modelsim does the right thing though - std.env.resolution_limit returns 100 ps and the VHDL model is simulated with 100 ps time precision.
Describe the solution you'd like
Please modify 5.2.4.2 to allow for finer resolution limits that match the SystemVerilog ones. Perhaps make it implementation dependent (yuck), worded something like "Implementations may optionally support additional resolution limits for compatibility with other languages outside the scope of IEEE-1076, but in all cases the resolution limit and the value returned by std.env.resolution_limit will be of type DELAY_LENGTH and greater than 0 fs."
Describe alternatives you've considered
No workarounds needed - it seems that simulator vendors already ignore 5.2.4.2 in favour of the SystemVerilog definition.