Allow subtypes of discrete types to specify the values, not just a range.

Doing some data generation for a testbench, I have a discrete type that specifies all the possible packet types that are available:

type pkt_t is (t0, t1, t2, t3, t4, t5, t6, t7);

for specific tests, I may only want to generate a subset of these, but currently (I can only use VHDL 2008, but I cant see any change in 2019), I can only specify a range of values:

subtype test2_pkt_st is pkt_t (t3 to t6);

If I want to exclude t4 and t5 I need all sorts of checks an balances in the test, or have methods that will then only generate specific types.

It might be easier to do this, if I could limit my subtype to a specific subset of the base type:

subtype test2_pkt_st is pkt_t (t3,t6);

This would be useful, as I could simply grab the 'left and 'right values, or 'range, from an object that comes through a subprogram as the base type, but the object is actually a constrained subtype.

eg.

procedure make_pkt ( variable pkt : out pkt_t ) is
begin
  ------
  for i in pkt'left to pkt'right loop
    -- do something for each packet type
  end loop;
end procedure;

---- in Testbench:
variable pkt_seq_item : test2_pkt_st;

---

make_pkt(pkt_seq_item);   -- only do packets t3 and t6