VHDL-2008 - clarification unary logical operator expression grammar is inconsistent with NOTE 2

From expressions section

expression ::=
 condition_operator primary
 | logical_expression

logical_expression ::=
 relation { and relation }
 | relation { or relation }
 | relation { xor relation }
 | relation [ nand relation ]
 | relation [ nor relation ]
 | relation { xnor relation }

relation ::=
 shift_expression [ relational_operator shift_expression ]

shift_expression ::=
 simple_expression [ shift_operator simple_expression ]

simple_expression ::=
 [ sign ] term { adding_operator term }

term ::=
 factor { multiplying_operator factor }

factor ::=
 primary [ ** primary ]
 | abs primary
 | not primary
 | logical_operator primary

In footnotes

NOTE 2 — The syntax for an expression involving a unary condition operator or unary logical operator in combination
with any other operator requires that the unary operator and its operand be a parenthesized expression. For example, the
expressions “(and A) and B” and “A and (and B)” are legal, whereas the expression “and A and B” and “A and and
B” are not. Similarly, “and (and A)” is legal, whereas “and and A” is not. An expression consisting only of a unary
condition operator or unary logical operator and its operand need not be parenthesized.

the example and A and B noted in note 2 as illegal, is legal according to the expression grammar, as per grammar and A := factor := term := simple_expression := shift_expression := relation

relation and A := logical_expression := expression

also the example, A and and B noted in note 2 as illegal is legal according to the expression grammar

Is Note 2 incorrect, or is the grammar wrong?

if unary condition operator and unary logical operator require being parenthesized as per note 2, I think the grammar should have unary logical operators, at the same location as the unary conditional operator

i.e. remove unary operator from

factor ::=
 primary [ ** primary ]
 | abs primary
 | not primary
-| logical_operator primary

add unary logical operator to expression at same location as unary condition operator

expression ::=
+ logical_operator primary
  | condition_operator primary
  | logical_expression