VHDL-2008 Clarification of use case for the type qualification and type conversion operation of an interface type

Looking at section "6.5.3 Interface type declarations" of the VHDL-2008 standard it states that:

The following operations are defined for the interface type:

• The basic operations of assignment, allocation, type qualification and type conversion
• The predefined equality (=) and inequality (/=) operators, implicitly declared as formal generic subprograms immediately following the interface type declaration in the enclosing interface list

It is clear to me how the equality and inequality operator can be used but I don't understand how the "type qualification" and "type conversion" can be used. It seems that my simulators (Questa Modelsim, Xcelium) always give an error message when I try to compile my example codes.

Can you please elaborate of what the intended use is of the "type qualification" and "type conversion" and what is expected to work? If I know that my interpretation of the standard is correct then I know at least that it's a tool issue

For example I will give the following pieces of code that use the "type qualification" and "type conversion" operation. From my understanding of the standard they should work

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity Submodule is
  generic (
    type t_Data
  );
  port (
    p_OutputData : out t_Data
  );
end entity Submodule;

architecture RTL of Submodule is

  constant c_Data : integer := 2;

begin
  
  -- Here I try to use a type conversion
  p_OutputData <= t_Data(c_Data);

end RTL;

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity TestLint is
  port (
  );
end entity TestLint;

architecture RTL of TestLint is

  type t_MyType is integer range 0 to 4;

begin

  inst_SubModule : entity work.Submodule(RTL)
    generic map (
      t_Data => t_MyType
    )
    port map (
      p_OutputData => open
    );

end RTL;

Second example:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity Submodule is
  generic (
    type t_Data
  );
  port (
    p_OutputData : out t_Data
  );
end entity Submodule;

architecture RTL of Submodule is

begin
  
  -- Here I try to use a type qualification
  p_OutputData <= t_Data'("010101");

end RTL;

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity TestSyntax is
  port (
    p_OutputData : out std_logic_vector(5 downto 0)
  );
end entity TestSyntax;

architecture RTL of TestSyntax is

begin

  inst_SubModule : entity work.Submodule(RTL)
    generic map (
      t_Data => std_logic_vector(5 downto 0)
    )
    port map (
      p_OutputData => p_OutputData
    );

end RTL;

P.S. Sorry if this is maybe not the best place to ask these questions but it seemed the only option left for further clarification of the VHDL standard