Instantiation of components/entities specified by a parameter (constant or generic)
During the last month, I talked about this with @JimLewis and @paebbels separatedly. I thought I had written it somewhere, but I cannot find it. Should anyone remember any related issue, please let me know.
Is your capability/feature request related to a problem?
The use case is the instantiation of a memory component, which requires a different architecture/declaration/implementation, depending on the target board, device or system design. Provided that a single entity and n
architectures exist, the capability request is being able to specify which architecture to use for an specific instantiation through a constant in a package or a (top-level) generic.
Describe the solution you'd like
My first impulse is to propose some alternative syntax for the case generate instantiate
situation, which allows specifying one architecture name along with an optional matching block
, all of them decorating a single generic map and port map. However, I would like to first be corrected if any of my assumptions below are wrong.
Describe alternatives you've considered
As far as I am aware, there are currently three alternatives, each with some advantages and caveats:
-
Classical: each entity can be declared as a component, by copying most of the declaration with minimal modifications. Then, a component can be instantiated as a black-box. Last, a configuration can be used for specifying which body (architecture) to use for each specific instantiation. The problem with this approach is that configurations are not composable. Hence, when a configuration is declared, all the "fields" need to be specified. Therefore, the number of different possible configurations grows exponentially with the number of instantiations in the design. Nevertheless, this approach is used in OSVVM with success.
-
Actual: since VHDL 2008, it is possible to instantiate an entity directly, without the intermediate component declaration. When doing so, the user can specify the architecture. However, the architecture must be a literal string, it cannot be a constant, a generic or any other parameter defined elsewhere. Therefore, in order to have multiple alternative instantiations
if generate
needs to be used. That is, if 3 different architectures are available for an entity, three instantiations are declared one after the other, andif generate
orcase generate
are used for deciding which is to be used. That is obviously verbose if you really want to instantiate three exactly equivalent architectures. However, it is also interesting because it allows to specify tweaks for each case (since eachcase
is effectively an isolatedblock
). This approach is used in PoC. -
Future: in VHDL 2019 conditional compilation was introduced. I wonder if that can be (mis)used for having
if
orcase
"defines" wrapping the first line of the entity instantiation only (neither the generic map nor the port map). Unfortunately, conditional compilation is not supported by most vendors yet, and particularly it's not supported in GHDL. Therefore, I could not do tests about how would this work.
Additional context
This is coming from a discussion in stnolting/neorv32. There are two memories (IMEM and DMEM) which need different architectures depending on the target board/device and design. Some targets use an inferred description, while others use the specific hard component templates.