Subprogram overloading, signals, variables

Is your capability/feature request related to a problem?

On a procedure with signal and variable output parameters, use the class of the object to differentiate which version of the procedure to use - perhaps also for impure functions with outputs.

WRT to synthesis, VHDL users who prefer to code piecewise are more likely to make use of procedures with signal outputs. OTOH VHDL users who prefer to code one large combinational logic process, are more likely to make use of procedures with variable outputs.

Describe the solution you'd like

Procedure Mux2 (
   A, B, Sel : std_logic ; 
  signal Y : out std_logic 
)

Procedure Mux2 (
  A, B, Sel : std_logic ; 
  variable Y : out std_logic
) ;

Describe alternatives you've considered

None.

Additional context

None