Automatic type deduction and/or ability to inspect type of un-evaluated expressions
We make heavy use of fixed-point types from VHDL 2008. One expressivity problem we very often run into is the need to determine the resulting type of a fixed point operation where we aren't resizing. We don't always know the size of the operand because we also make heavy use of unconstrained types. Even if we did know the sizes, requiring the user to memorize the sizing rules and repeat the computation, only to punish them if they get it wrong, is not great. For example:
entity thingy is
port (
signal a : sfixed;
signal b : sfixed;
);
end entity thingy;
architecture rtl of thingy is
signal res : sfixed(...); -- must compute range here
begin
res <= a + b;
end architecture rtl;
Currently in VHDL what we do is use a support library we developed comprising function that takes fixed point signals and an operation string and repeats the output sizing returning a proper "size_res" fixed point type.
signal res : sfixed := FixedPointResultType(a, '+', b);
We have datatype models of fixed points in C++, and C++ allows use to auto
or decltype
to avoid the nonsense I mentioned before.
template <int L, int R>
class sfixed { ... };
template <
typename AType
typename BType
>
void thingy(AType a, BType b)
{
auto res = a + b; -- just `auto` so we don't have to compute the type ourselves
decltype(a + b) res2 = a + b; -- equivalent, but worse
}
There are multiple possible ways to handle this:
- Support type deduction, possibly by introducing
auto
as a type. This would only work if all assignments to the signal were of the same type. This may also partially apply to #69. - Support an interface to obtain the type of a value or expression, similar to
decltype
. This may also apply to #48. - Support using unconstrained types in declarative regions, to be constrained by usage, essentially a limited form of option 1 and similar to usage of unconstrained ports.