Sequential Signal Declarations

Declare signals in sequential code and use attributes such as 'transaction in subprograms.

Using 'transaction in subprograms seems to be important.

Describe the solution you'd like

Need to complete examples Example 1: Encapsulating an entire feature. In clocked process.
A) Parallel in serial out shift register B) Variable delay element

Encapsulating subprograms with signal outputs. Application testbench procedures in which the delay is there already. Limitations: Signals need to be updated before read - hence, the procedure Will have a wait statement that allows the signal to update

Original Proposal

See http://www.eda-twiki.org/cgi-bin/view.cgi/P1076/SequentialSignal.

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Proposal Editing Information
Who Updates: JimLewis, , ...
Date Proposed: 2012-08-19
Date Last Updated: 2012-08-19
Priority:
Complexity:
Focus: Testbench

Requirement Summary

Declarations of signals in subprograms and processes.

Chaining together transaction based subprograms that have signal IO. Signal as a local in a clocked process - flip-flop example.

Use Model:

Old use model here was incorrect and was removed

Questions

General Comments

14.7 Dynamic elaboration

...

NOTE 1—It is a consequence of these rules that declarative items appearing within the declarative part of a subprogram body are elaborated each time the corresponding subprogram is called; thus, successive elaborations of a given declarative item appearing in such a place may create items with different characteristics. For example, successive elaborations of the same subtype declaration appearing in a subprogram body may create subtypes with different constraints.

It doesn't seem possible to dynamically elaborate signals. It would be a terrible simulator complication to be able to add or remove signals and queues from an elaborated design model dynamically. A process statement (a procedure, not a function which is an expression) communicating to the process through signals requires a process statement that implies hierarchy (a block statement) and promotion of a sequential procedure statement to a concurrent procedure statement.. We already have under utilized block statements. This doesn't appear to be something VHDL needs to support and would require devolving such process statements into block statements and process statements for simulation, essentially expressing that level of hierarchy you're trying to imply but avoid.

-- DavidKoontz - 2014-12-04

Supporters

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-- JimLewis - 2014-12-04

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