User-Guide-Interface-UVC-Generation.md

 This section explains how to use the Interface UVC generation feature.
+When launching the application, the Interface Verification Component Wizard opens and the following screen is what we'll see:
+![00_-_signal_map_declaration](uploads/c94baff34070f8cce1b2e83b0202f292/00_-_signal_map_declaration.png)
  
-**Configuring the UVC Name**
+The subsequent sections describe the information presented and what is mandatory and optional.
+
+**Configuring the UVC Name (Mandatory Fields)**
 
 In UVM, each verification component has a prefix combination that describes exactly which company, or group within a company, and the protocol are called.
 This configuration is handled with the text fields "Group Name" and "Protocol Name".
 
 Example:
 
-Let's assume I am creating a verification component that describes an I2C protocol. In that case, I am using my name's initials and the protocol name:
+Let's assume we are creating a verification component that describes a custom handshake protocol. In that case, I am using my name's initials and the protocol name:
 ```
 Group Name   Protocol Name
-db           i2c
+db           handshake
 ```
 
 
-**Configuring the Clock Domain**
+**Configuring the Clock Domain (Mandatory Fields)**
+
+Creating the clocking details consists of three parameters:
+1. Testbench Clock Name: This is the name used within the UVM testbench domain.
+2. HDL Clock Name      : This is the name used within the HDL top-level testbench harness
+3. Clock Sensitivity   : This may assume any of three values:
+*  Rising Edge, which means that each signal will be sampled/driven at the clock's transition from 0 to 1.
+*  Falling Edge, which means that each signal will be sampled/driven at the clock's transition from 1 to 0.
+*  Rising and Falling Edge, which indicates that whenever the clock signal transitions, then each signal's value will be sampled/driven
+*  Asynchronous, this means there is effectively no clock. This option should only be used in very rare cases and only if you truly understand the implications of asynchronous protocol design.
+
 
+**Configuring the Reset Domain (Mandatory Fields)**
 
-**Configuring the Reset Domain**
+Creating the reset details consists of three parameters:
+1. Testbench Reset Name: This is the reset name used within the UVM testbench domain.
+2. HDL Reset Name      : This is the reset name used within the HDL top-level testbench harness.
+3. Reset-Active        : This may assume any of the two values:
+* Active-Low. which is used to indicate that low-level (value 0) reset is used to reset the design.
+* Active-High, which is used to indicate that the high-level (value 1) reset is used to reset the design.
 
 
 **Adding Signal Descriptions**