@@ -84,29 +84,69 @@ By clicking on the "Data Item" tab, you will be able to define the base informat
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@@ -84,29 +84,69 @@ By clicking on the "Data Item" tab, you will be able to define the base informat
Please note that only the columns changed in this particular view, adding and removing fields within this tab works the same way as it does in the "Interface Signals" tab.
Please note that only the columns changed in this particular view, adding and removing fields within this tab works the same way as it does in the "Interface Signals" tab.
The Name column indicates the name of the field that is used within the transaction.
The *Name* column indicates the name of the field that is used within the transaction.
The column with the die icon indicates if a field is supposed to be generated with random values. If the check-mark is set, then generation is enabled for that field, which is the default. If a field in this column is unchecked, then generation and its according randomization is disabled.
The column with the *die icon* indicates if a field is supposed to be generated with random values. If the check-mark is set, then generation is enabled for that field, which is the default. If a field in this column is unchecked, then generation and its according randomization is disabled.
The column with the green rectangular line indicates a waveform clock signal. If a field in this column is checked, then this field is part of the protocol that is physically transferred to the HDL domain. If unchecked, then this field is considered to be a virtual field that shall not be driven on the wire.
The column with the *green rectangular line indicates a waveform clock signal*. If a field in this column is checked, then this field is part of the protocol that is physically transferred to the HDL domain. If unchecked, then this field is considered to be a virtual field that shall not be driven on the wire.
The Type column is very similar to the signal map declaration Type column. The only difference is that the drop-down menu now also offers the 'time' type, which is useful to store simulation time-stamps in a transaction item.
The *Type* column is very similar to the signal map declaration Type column. The only difference is that the drop-down menu now also offers the 'time' type, which is useful to store simulation time-stamps in a transaction item.
The Bit Width column carries the exact same information as the signal map's Bit Width column. It contains the size of a vector in bits that is used to describe the signal's value space.
The *Bit Width* column carries the exact same information as the signal map's Bit Width column. It contains the size of a vector in bits that is used to describe the signal's value space.
The n-Dimensions column indicates how many dimensions the array has. If the 0 value is selected, then the field is not modelled as a list/array type. By increasing the number of this field, another dimension is added to the list type.
The *n-Dimensions* column indicates how many dimensions the array has. If the 0 value is selected, then the field is modelled as a single field. By increasing the number of this field, another dimension is added to the list type.
Example:
*Example*:
A field that is a single list/array is indicated by the value 1 and as such there is a dynamic list of one dimension
A field that is a single list/array is indicated by the value 1 and as such there is a dynamic list of one dimension
A field declared with the number 3 in this column is a 3-dimensional list/array. This field is then addressable in three dimensions <field_name>[2][5][1] to point to the third list's fifth sublist's second element :-)
A field declared with the number 3 in this column is a 3-dimensional list/array. This field is then addressable in three dimensions <field_name>[2][5][1] to point to the third list's fifth sublist's second element :-)
**Adding Configuration Fields (Optional Fields)**
**Adding Configuration Fields (Optional Fields)**
SpecEx generates configuration objects that are passed as a single object, to allow configuring a global information throughout the environment. If you require to add configuration options that are relevant to the complete testbench and each instantiation of the testbench's protocol agents, then it is recommended you add these options to the "Global Configuration" tab table.
SpecEx generates *configuration objects* that are passed as a single object, to allow configuring a *global information throughout the environment*. If you require to add configuration options that are relevant to the complete testbench and each instantiation of the testbench's protocol agents, then it is recommended you add these options to the "Global Configuration" tab table.
Additionally, you can define configuration fields that are instantiated per agent instance. This allows to configure fine-granular options per interface instance, such as bit-widths, timings, etc. If you require to add this kind of information, please select the "Interface Configuration" and proceed to add fields in here.
Additionally, you can define *configuration fields* that are instantiated *per agent instance*. This allows to configure fine-granular options per interface instance, such as bit-widths, timings, etc. If you require to add this kind of information, please select the "Interface Configuration" and proceed to add fields in here.
**Adding Custom Enumerated Types**
**Adding Custom Enumerated Types**
**Waveform Editor**
**Waveform Editor (Optional for Code Generation)**
The Waveform Editor tab provides you the means to create waveform scenarios with the following screen:
The waveform editor may provide a quick-start to driving stimulus into the design and should allow every HDL and HVL expert to model the signal flow for scenarios.
A scenario is defined as which signals are driven across the number of clocks in this view.
The clock, reset and other signal names are being extracted directly from the "Interface Signal" tab configuration. Once you add a new interface signal, it automatically shows up in this view. If you remove a signal from the interface signals, also that signal will be removed from the waveform view.
The first two lines in this view are always the clock and then the reset signal. Both signals are marked as Read, because those signals are never allowed to be driven by the UVC.
The "Access" column indicates if a signal is to be "Driven" or "Read".
Any signal, except for clock and reset, can be selected to be either driven in the scenario or just being left in read-only mode, which means the signal is ignored for signal generation.
The number of columns indicates how many cycles are used to model/drive the scenario. Each column indicates a single clock cycle.
=> By clicking "Reduce Time" you can remove cycles from the current scenario model.
=> By clicking "Add Time" you can add more cycles to the current scenario model.
The two signal-types that are currently supported are single-bit and vector signals. This information is derived from the declaration of the signals as defined in the "Interface Signals" tab.
=> For single-bit signals you can left-click on any of the cells to change the values. Possible values are only 0s and 1s.
=> For vectored signals, you can left-click on any of the cells to indicate that a new value will be set. Currently there is no support for directly setting the values of a vectored signal.
Once you are done modelling a scenario, you must provide a name in the Current Scenario Name line and click the "New" button.
To remove an already configured scenario, you have to select a scenario from the list next to the scenario name line and then click the "Delete" button.
**Generating the UVC**
To create the executable simulation and verification code-base, click the "Generate" button.
This will validate the fields in your environment first. If information is missing, then you will be prompted to resolve all red colored fields and click generate again.
Once the validated model is ready for generation you will be asked to point to a location of where the code is to be added to your file system.
Adding the code to your file system is done by the generator to create a folder with the name of the UVC, based on the "Group Name" and "Protocol Name":
<selected_folder>/<group_name>_<protocol_name>
**WARNING:
The code generation will overwrite anything and everything without asking for confirmation, if that folder or the files already exist!!!!!!**
**Simulating the UVC**
If your code has been successfully generated and you have Cadence Xcelium executables in your Linux environment PATH variable, then you can click the "Simulate" button and a simulation will be launched in GUI mode.
