@@ -4,6 +4,11 @@ When launching the application, the Interface Verification Component Wizard open
The subsequent sections describe the information presented and what is mandatory and optional.
**Disclaimer:**
The information you need to create a UVM verification component (UVC) should always be inferred from the documentation or specification. It is the verification engineer's responsibility to always get the latest specifications and ensure the correct implementation of the protocol.
Please keep in mind that white-space characters are not allowed for any of the field names as shown below.
**Configuring the UVC Name (Mandatory Fields)**
In UVM, each verification component has a prefix combination that describes exactly which company, or group within a company, and the protocol are called.
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@@ -20,10 +25,10 @@ db handshake
**Configuring the Clock Domain (Mandatory Fields)**
Creating the clocking details consists of three parameters:
1. Testbench Clock Name: This is the name used within the UVM testbench domain.
2. HDL Clock Name : This is the name used within the HDL top-level testbench harness
3. Clock Sensitivity : This may assume any of three values:
Creating the clocking details consists of **three parameters**:
1.**Testbench Clock Name**: This is the name used within the UVM testbench domain.
2.**HDL Clock Name **: This is the name used within the HDL top-level testbench harness
3.**Clock Sensitivity **: This may assume any of three values:
* Rising Edge , which means that each signal will be sampled/driven at the clock's transition from 0 to 1.
* Falling Edge, which means that each signal will be sampled/driven at the clock's transition from 1 to 0.
* Rising and Falling Edge, which indicates that whenever the clock signal transitions, then each signal's value will be sampled/driven
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@@ -40,8 +45,30 @@ Creating the reset details consists of three parameters:
* Active-High, which is used to indicate that the high-level (value 1) reset is used to reset the design.
**Adding Signal Descriptions**
**Adding Signal Descriptions (Mandatory Fields)**
Each signal used in the UVC is modelled to match the properties of the HDL counterpart. As such, we need information on what that signal may need to be modelled:
The Name column contains the signal's name as it is used in the UVM language domain.
The Type column contains the signal's data type. To make it easier, a drop-down list of predefined types is present, but it is also possible to add a new signal type, by typing in a user-defined type.
Predefined types are:
* bit, indicating the signal is only a single bit-wide
* uint, indicating the signal may be of an unsigned integer vector type. If uint is chosen, then the Width column actually defines the vector width.
* real, indicating the signal is a floating point data type.
A note on User-Defined Types:
Please keep in mind that this user-defined type must also be added to the enumerated type database of that UVC, by clicking the "Type Edit" button.
The Width column contains a numeric value, indicating the bit-width of the vector of the given Type column.
The Access direction is provided as a drop-down box, which contains three options:
* HDL Read/Write: Selecting this option enables the UVC to read values from the HDL domain and also drive values into the HDL domain.
* HDL Read: Selecting this option enables the UVC to only read values from the HDL domain. Writing values to the HDL domain is not possible if this option is selected.
* HDL Write: Selecting this option enables the UVC to only write values to the HDL domain. Reading values from the HDL domain is not possible if this option is selected.
The HDL Name column indicates the default name of the signal in the HDL top-level testbench harness. This value is only given to provide a default name, so it is possible to create a complete and executable testbench package.
Adding New Signals:
To put multiple signals in your protocol UVC, you can either
